📄 decoder48.rpt
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Device-Specific Information: d:\zzr\eda\shizhong\decoder48.rpt
decoder48
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 11/ 48( 22%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zzr\eda\shizhong\decoder48.rpt
decoder48
** EQUATIONS **
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
-- Node name is 'seg0'
-- Equation name is 'seg0', type is output
seg0 = _LC4_A24;
-- Node name is 'seg1'
-- Equation name is 'seg1', type is output
seg1 = _LC8_A20;
-- Node name is 'seg2'
-- Equation name is 'seg2', type is output
seg2 = _LC1_A24;
-- Node name is 'seg3'
-- Equation name is 'seg3', type is output
seg3 = _LC7_A20;
-- Node name is 'seg4'
-- Equation name is 'seg4', type is output
seg4 = _LC2_A24;
-- Node name is 'seg5'
-- Equation name is 'seg5', type is output
seg5 = _LC6_A20;
-- Node name is 'seg6'
-- Equation name is 'seg6', type is output
seg6 = _LC5_A24;
-- Node name is 'seg7'
-- Equation name is 'seg7', type is output
seg7 = GND;
-- Node name is ':23'
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = LCELL( _EQ001);
_EQ001 = !d0 & !d1 & !d2 & !d3;
-- Node name is ':28'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ002);
_EQ002 = d0 & !d1 & !d2 & !d3;
-- Node name is ':33'
-- Equation name is '_LC2_A20', type is buried
_LC2_A20 = LCELL( _EQ003);
_EQ003 = !d0 & d1 & !d2 & !d3;
-- Node name is ':38'
-- Equation name is '_LC3_A20', type is buried
_LC3_A20 = LCELL( _EQ004);
_EQ004 = d0 & d1 & !d2 & !d3;
-- Node name is ':43'
-- Equation name is '_LC8_A24', type is buried
_LC8_A24 = LCELL( _EQ005);
_EQ005 = !d0 & !d1 & d2 & !d3;
-- Node name is ':171'
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ006);
_EQ006 = !d0 & d2 & !d3
# !d1 & d2 & !d3
# !d0 & d1 & !d3
# d1 & !d2 & !d3
# !d1 & !d2 & d3;
-- Node name is ':190'
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ007);
_EQ007 = !d1 & !d2 & d3
# !d0 & d2 & !d3
# !d1 & d2 & !d3;
-- Node name is ':202'
-- Equation name is '_LC6_A20', type is buried
_LC6_A20 = LCELL( _EQ008);
_EQ008 = _LC4_A20 & _LC6_A24
# _LC1_A20;
-- Node name is '~204~1'
-- Equation name is '~204~1', location is LC4_A20, type is buried.
-- synthesized logic cell
!_LC4_A20 = _LC4_A20~NOT;
_LC4_A20~NOT = LCELL( _EQ009);
_EQ009 = _LC2_A20
# _LC3_A20
# _LC7_A24;
-- Node name is ':235'
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ010);
_EQ010 = !d0 & !d2 & !d3
# !d0 & !d1 & !d2
# !d0 & d1 & !d3;
-- Node name is ':253'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ011);
_EQ011 = d0 & !d1 & d2 & !d3
# !d0 & !d1 & !d2 & d3
# !d0 & d1 & d2 & !d3;
-- Node name is ':262'
-- Equation name is '_LC5_A20', type is buried
_LC5_A20 = LCELL( _EQ012);
_EQ012 = _LC2_A20
# _LC3_A20
# _LC3_A24 & !_LC8_A24;
-- Node name is ':268'
-- Equation name is '_LC7_A20', type is buried
_LC7_A20 = LCELL( _EQ013);
_EQ013 = _LC5_A20 & !_LC7_A24
# _LC1_A20;
-- Node name is ':301'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ014);
_EQ014 = !d1 & !d3
# d2 & !d3
# !d1 & !d2
# d0 & !d3;
-- Node name is ':324'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = LCELL( _EQ015);
_EQ015 = !d1 & !d2 & d3
# d0 & d1 & d2 & !d3;
-- Node name is ':334'
-- Equation name is '_LC8_A20', type is buried
_LC8_A20 = LCELL( _EQ016);
_EQ016 = _LC1_A20
# _LC8_A24
# !_LC4_A20
# _LC1_A18;
-- Node name is ':367'
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ017);
_EQ017 = !d0 & !d2 & !d3
# d0 & d2 & !d3
# !d0 & !d1 & !d2
# !d1 & !d2 & d3
# d1 & !d3;
Project Information d:\zzr\eda\shizhong\decoder48.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,786K
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