📄 second.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 6/ 96( 6%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zzr\eda\shizhong\second.rpt
second
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CP
Device-Specific Information: d:\zzr\eda\shizhong\second.rpt
second
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 Rd
Device-Specific Information: d:\zzr\eda\shizhong\second.rpt
second
** EQUATIONS **
CP : INPUT;
EN : INPUT;
Rd : INPUT;
-- Node name is 'CO'
-- Equation name is 'CO', type is output
CO = _LC2_C10;
-- Node name is ':20' = 'QN0'
-- Equation name is 'QN0', location is LC6_B12, type is buried.
QN0 = DFFE( _EQ001, GLOBAL( CP), GLOBAL( Rd), VCC, VCC);
_EQ001 = !EN & QN0
# EN & !QN0;
-- Node name is ':19' = 'QN1'
-- Equation name is 'QN1', location is LC2_B12, type is buried.
QN1 = DFFE( _EQ002, GLOBAL( CP), GLOBAL( Rd), VCC, VCC);
_EQ002 = !_LC7_B12 & !QN0 & QN1
# EN & !_LC7_B12 & QN0 & !QN1
# !EN & QN1;
-- Node name is ':18' = 'QN2'
-- Equation name is 'QN2', location is LC8_B12, type is buried.
QN2 = DFFE( _EQ003, GLOBAL( CP), GLOBAL( Rd), VCC, VCC);
_EQ003 = !_LC4_B12 & !_LC7_B12 & QN2
# EN & _LC4_B12 & !_LC7_B12 & !QN2
# !EN & QN2;
-- Node name is ':17' = 'QN3'
-- Equation name is 'QN3', location is LC3_B12, type is buried.
QN3 = DFFE( _EQ004, GLOBAL( CP), GLOBAL( Rd), VCC, VCC);
_EQ004 = EN & _LC5_B12 & !_LC7_B12
# !EN & QN3;
-- Node name is ':16' = 'QN4'
-- Equation name is 'QN4', location is LC1_B12, type is buried.
QN4 = DFFE( _EQ005, GLOBAL( CP), GLOBAL( Rd), VCC, VCC);
_EQ005 = !_LC7_B12 & QN4
# EN & _LC7_B12 & !QN4
# !EN & QN4;
-- Node name is ':15' = 'QN5'
-- Equation name is 'QN5', location is LC1_C6, type is buried.
QN5 = DFFE( _EQ006, GLOBAL( CP), GLOBAL( Rd), VCC, VCC);
_EQ006 = EN & _LC2_C6
# !_LC7_B12 & QN5
# !EN & QN5;
-- Node name is ':14' = 'QN6'
-- Equation name is 'QN6', location is LC5_C6, type is buried.
QN6 = DFFE( _EQ007, GLOBAL( CP), GLOBAL( Rd), VCC, VCC);
_EQ007 = EN & _LC4_C6
# !_LC7_B12 & QN6
# !EN & QN6;
-- Node name is ':13' = 'QN7'
-- Equation name is 'QN7', location is LC7_C6, type is buried.
QN7 = DFFE( _EQ008, GLOBAL( CP), GLOBAL( Rd), VCC, VCC);
_EQ008 = EN & _LC8_C6
# !_LC7_B12 & QN7
# !EN & QN7;
-- Node name is 'SH0'
-- Equation name is 'SH0', type is output
SH0 = QN4;
-- Node name is 'SH1'
-- Equation name is 'SH1', type is output
SH1 = QN5;
-- Node name is 'SH2'
-- Equation name is 'SH2', type is output
SH2 = QN6;
-- Node name is 'SH3'
-- Equation name is 'SH3', type is output
SH3 = QN7;
-- Node name is 'SL0'
-- Equation name is 'SL0', type is output
SL0 = QN0;
-- Node name is 'SL1'
-- Equation name is 'SL1', type is output
SL1 = QN1;
-- Node name is 'SL2'
-- Equation name is 'SL2', type is output
SL2 = QN2;
-- Node name is 'SL3'
-- Equation name is 'SL3', type is output
SL3 = QN3;
-- Node name is '|LPM_ADD_SUB:281|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C6', type is buried
_LC6_C6 = LCELL( _EQ009);
_EQ009 = QN4 & QN5;
-- Node name is '|LPM_ADD_SUB:409|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B12', type is buried
_LC4_B12 = LCELL( _EQ010);
_EQ010 = QN0 & QN1;
-- Node name is '|LPM_ADD_SUB:409|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = LCELL( _EQ011);
_EQ011 = !QN1 & QN3
# !QN0 & QN3
# !QN2 & QN3
# QN0 & QN1 & QN2 & !QN3;
-- Node name is ':109'
-- Equation name is '_LC7_B12', type is buried
!_LC7_B12 = _LC7_B12~NOT;
_LC7_B12~NOT = LCELL( _EQ012);
_EQ012 = !QN3
# QN2
# QN1
# !QN0;
-- Node name is ':179'
-- Equation name is '_LC3_C6', type is buried
!_LC3_C6 = _LC3_C6~NOT;
_LC3_C6~NOT = LCELL( _EQ013);
_EQ013 = QN7
# !QN6
# QN5
# !QN4;
-- Node name is '~456~1'
-- Equation name is '~456~1', location is LC1_C10, type is buried.
-- synthesized logic cell
_LC1_C10 = LCELL( _EQ014);
_EQ014 = !_LC3_C6 & _LC7_B12;
-- Node name is ':456'
-- Equation name is '_LC8_C6', type is buried
_LC8_C6 = LCELL( _EQ015);
_EQ015 = _LC1_C10 & !_LC6_C6 & QN7
# _LC1_C10 & !QN6 & QN7
# _LC1_C10 & _LC6_C6 & QN6 & !QN7;
-- Node name is ':462'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = LCELL( _EQ016);
_EQ016 = _LC1_C10 & !QN5 & QN6
# _LC1_C10 & !QN4 & QN6
# _LC1_C10 & QN4 & QN5 & !QN6;
-- Node name is ':468'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = LCELL( _EQ017);
_EQ017 = _LC1_C10 & !QN4 & QN5
# _LC1_C10 & QN4 & !QN5;
-- Node name is ':606'
-- Equation name is '_LC2_C10', type is buried
_LC2_C10 = LCELL( _EQ018);
_EQ018 = EN & _LC3_C6 & _LC7_B12;
Project Information d:\zzr\eda\shizhong\second.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,735K
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