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📄 shiz.rpt

📁 数字钟的VHDL源程序
💻 RPT
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_LC4_A16 = LCELL( _EQ068);
  _EQ068 = !_LC1_A17 & !_LC7_A17 &  _LC8_A17 &  _LC8_A21;

-- Node name is '|MUX6:19|:385' 
-- Equation name is '_LC6_A16', type is buried 
_LC6_A16 = LCELL( _EQ069);
  _EQ069 = !_LC1_A17 &  _LC3_A16 &  _LC7_A17 &  _LC8_A17;

-- Node name is '|MUX6:19|:386' 
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = LCELL( _EQ070);
  _EQ070 =  _LC3_A20 &  _LC4_A17
         #  _LC4_A16 & !_LC4_A17
         # !_LC4_A17 &  _LC6_A16;

-- Node name is '|MUX6:19|:389' 
-- Equation name is '_LC2_A16', type is buried 
_LC2_A16 = LCELL( _EQ071);
  _EQ071 = !_LC1_A22 &  _LC7_A16
         #  _LC1_A22 &  _LC5_A14;

-- Node name is '|MUX6:19|:392' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ072);
  _EQ072 =  _LC2_A16 & !_LC3_A17
         #  _LC3_A17 &  _LC3_A19;

-- Node name is '|MUX6:19|:395' 
-- Equation name is '_LC7_A23', type is buried 
_LC7_A23 = LCELL( _EQ073);
  _EQ073 = !_LC4_A22 &  _LC5_A23
         #  _LC4_A22 &  _LC4_A24;

-- Node name is '|MUX6:19|:405' 
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = LCELL( _EQ074);
  _EQ074 = !_LC1_A17 &  _LC3_A21 & !_LC7_A17 &  _LC8_A17;

-- Node name is '|MUX6:19|:406' 
-- Equation name is '_LC6_A17', type is buried 
_LC6_A17 = LCELL( _EQ075);
  _EQ075 = !_LC1_A17 &  _LC5_A18 &  _LC7_A17 &  _LC8_A17;

-- Node name is '|MUX6:19|:407' 
-- Equation name is '_LC2_A17', type is buried 
_LC2_A17 = LCELL( _EQ076);
  _EQ076 =  _LC1_A20 &  _LC4_A17
         # !_LC4_A17 &  _LC5_A17
         # !_LC4_A17 &  _LC6_A17;

-- Node name is '|MUX6:19|:410' 
-- Equation name is '_LC4_A14', type is buried 
_LC4_A14 = LCELL( _EQ077);
  _EQ077 = !_LC1_A22 &  _LC2_A17
         #  _LC1_A22 &  _LC7_A14;

-- Node name is '|MUX6:19|:413' 
-- Equation name is '_LC8_A23', type is buried 
_LC8_A23 = LCELL( _EQ078);
  _EQ078 = !_LC3_A17 &  _LC4_A14
         #  _LC3_A17 &  _LC5_A19;

-- Node name is '|MUX6:19|:416' 
-- Equation name is '_LC6_A23', type is buried 
_LC6_A23 = LCELL( _EQ079);
  _EQ079 = !_LC4_A22 &  _LC8_A23
         #  _LC4_A22 &  _LC6_A24;

-- Node name is '|MUX6:19|:426' 
-- Equation name is '_LC8_A18', type is buried 
_LC8_A18 = LCELL( _EQ080);
  _EQ080 = !_LC1_A17 &  _LC5_A16 & !_LC7_A17 &  _LC8_A17;

-- Node name is '|MUX6:19|:427' 
-- Equation name is '_LC6_A18', type is buried 
_LC6_A18 = LCELL( _EQ081);
  _EQ081 = !_LC1_A17 &  _LC4_A18 &  _LC7_A17 &  _LC8_A17;

-- Node name is '|MUX6:19|:428' 
-- Equation name is '_LC7_A18', type is buried 
_LC7_A18 = LCELL( _EQ082);
  _EQ082 =  _LC1_A15 &  _LC4_A17
         # !_LC4_A17 &  _LC6_A18
         # !_LC4_A17 &  _LC8_A18;

-- Node name is '|MUX6:19|:435' 
-- Equation name is '_LC4_A23', type is buried 
_LC4_A23 = LCELL( _EQ083);
  _EQ083 =  _LC2_A24 &  _LC3_A17;

-- Node name is '|MUX6:19|:436' 
-- Equation name is '_LC3_A23', type is buried 
_LC3_A23 = LCELL( _EQ084);
  _EQ084 = !_LC1_A22 & !_LC3_A17 &  _LC7_A18
         #  _LC1_A22 &  _LC2_A14 & !_LC3_A17;

-- Node name is '|MUX6:19|:437' 
-- Equation name is '_LC1_A23', type is buried 
_LC1_A23 = LCELL( _EQ085);
  _EQ085 =  _LC3_A23 & !_LC4_A22
         # !_LC4_A22 &  _LC4_A23
         #  _LC3_A24 &  _LC4_A22;

-- Node name is '|QUDOU:4|:6' = '|QUDOU:4|cp' 
-- Equation name is '_LC2_A11', type is buried 
_LC2_A11 = DFFE( _EQ086, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ086 =  AM &  _LC1_A11 &  _LC3_A11;

-- Node name is '|QUDOU:4|:5' = '|QUDOU:4|js0' 
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = DFFE( _EQ087, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ087 =  AM &  _LC3_A11
         #  AM & !_LC1_A11;

-- Node name is '|QUDOU:4|:4' = '|QUDOU:4|js1' 
-- Equation name is '_LC3_A11', type is buried 
_LC3_A11 = DFFE( _EQ088, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ088 =  AM &  _LC3_A11
         #  AM &  _LC1_A11;

-- Node name is '|QUDOU:8|:6' = '|QUDOU:8|cp' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = DFFE( _EQ089, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ089 =  AH &  _LC2_A13 &  _LC3_A13;

-- Node name is '|QUDOU:8|:5' = '|QUDOU:8|js0' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = DFFE( _EQ090, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ090 =  AH &  _LC3_A13
         #  AH & !_LC2_A13;

-- Node name is '|QUDOU:8|:4' = '|QUDOU:8|js1' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = DFFE( _EQ091, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ091 =  AH &  _LC3_A13
         #  AH &  _LC2_A13;

-- Node name is '|SECOND:11|LPM_ADD_SUB:281|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A23', type is buried 
_LC2_A23 = LCELL( _EQ092);
  _EQ092 =  _LC2_A24 &  _LC5_A19;

-- Node name is '|SECOND:11|LPM_ADD_SUB:409|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A24', type is buried 
_LC7_A24 = LCELL( _EQ093);
  _EQ093 =  _LC3_A24 &  _LC6_A24;

-- Node name is '|SECOND:11|LPM_ADD_SUB:409|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A24', type is buried 
_LC1_A24 = LCELL( _EQ094);
  _EQ094 = !_LC3_A24 &  _LC5_A24
         #  _LC5_A24 & !_LC6_A24
         # !_LC4_A24 &  _LC5_A24
         #  _LC3_A24 &  _LC4_A24 & !_LC5_A24 &  _LC6_A24;

-- Node name is '|SECOND:11|:20' = '|SECOND:11|QN0' 
-- Equation name is '_LC3_A24', type is buried 
_LC3_A24 = DFFE( _EQ095, GLOBAL( CP), GLOBAL( RD),  VCC,  VCC);
  _EQ095 = !EN &  _LC3_A24
         #  EN & !_LC3_A24;

-- Node name is '|SECOND:11|:19' = '|SECOND:11|QN1' 
-- Equation name is '_LC6_A24', type is buried 
_LC6_A24 = DFFE( _EQ096, GLOBAL( CP), GLOBAL( RD),  VCC,  VCC);
  _EQ096 =  EN &  _LC3_A24 & !_LC6_A24 & !_LC8_A24
         # !_LC3_A24 &  _LC6_A24 & !_LC8_A24
         # !EN &  _LC6_A24;

-- Node name is '|SECOND:11|:18' = '|SECOND:11|QN2' 
-- Equation name is '_LC4_A24', type is buried 
_LC4_A24 = DFFE( _EQ097, GLOBAL( CP), GLOBAL( RD),  VCC,  VCC);
  _EQ097 =  _LC4_A24 & !_LC7_A24 & !_LC8_A24
         #  EN & !_LC4_A24 &  _LC7_A24 & !_LC8_A24
         # !EN &  _LC4_A24;

-- Node name is '|SECOND:11|:17' = '|SECOND:11|QN3' 
-- Equation name is '_LC5_A24', type is buried 
_LC5_A24 = DFFE( _EQ098, GLOBAL( CP), GLOBAL( RD),  VCC,  VCC);
  _EQ098 =  EN &  _LC1_A24 & !_LC8_A24
         # !EN &  _LC5_A24;

-- Node name is '|SECOND:11|:16' = '|SECOND:11|QN4' 
-- Equation name is '_LC2_A24', type is buried 
_LC2_A24 = DFFE( _EQ099, GLOBAL( CP), GLOBAL( RD),  VCC,  VCC);
  _EQ099 =  _LC2_A24 & !_LC8_A24
         #  EN & !_LC2_A24 &  _LC8_A24
         # !EN &  _LC2_A24;

-- Node name is '|SECOND:11|:15' = '|SECOND:11|QN5' 
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = DFFE( _EQ100, GLOBAL( CP), GLOBAL( RD),  VCC,  VCC);
  _EQ100 =  EN &  _LC7_A19
         #  _LC5_A19 & !_LC8_A24
         # !EN &  _LC5_A19;

-- Node name is '|SECOND:11|:14' = '|SECOND:11|QN6' 
-- Equation name is '_LC3_A19', type is buried 
_LC3_A19 = DFFE( _EQ101, GLOBAL( CP), GLOBAL( RD),  VCC,  VCC);
  _EQ101 =  EN &  _LC8_A19
         #  _LC3_A19 & !_LC8_A24
         # !EN &  _LC3_A19;

-- Node name is '|SECOND:11|:13' = '|SECOND:11|QN7' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = DFFE( _EQ102, GLOBAL( CP), GLOBAL( RD),  VCC,  VCC);
  _EQ102 =  EN &  _LC6_A19
         #  _LC1_A19 & !_LC8_A24
         # !EN &  _LC1_A19;

-- Node name is '|SECOND:11|:109' 
-- Equation name is '_LC8_A24', type is buried 
!_LC8_A24 = _LC8_A24~NOT;
_LC8_A24~NOT = LCELL( _EQ103);
  _EQ103 = !_LC5_A24
         # !_LC3_A24
         #  _LC4_A24
         #  _LC6_A24;

-- Node name is '|SECOND:11|:179' 
-- Equation name is '_LC2_A19', type is buried 
!_LC2_A19 = _LC2_A19~NOT;
_LC2_A19~NOT = LCELL( _EQ104);
  _EQ104 =  _LC1_A19
         # !_LC2_A24
         # !_LC3_A19
         #  _LC5_A19;

-- Node name is '|SECOND:11|~456~1' 
-- Equation name is '_LC4_A19', type is buried 
-- synthesized logic cell 
_LC4_A19 = LCELL( _EQ105);
  _EQ105 = !_LC2_A19 &  _LC8_A24;

-- Node name is '|SECOND:11|:456' 
-- Equation name is '_LC6_A19', type is buried 
_LC6_A19 = LCELL( _EQ106);
  _EQ106 =  _LC1_A19 & !_LC2_A23 &  _LC4_A19
         #  _LC1_A19 & !_LC3_A19 &  _LC4_A19
         # !_LC1_A19 &  _LC2_A23 &  _LC3_A19 &  _LC4_A19;

-- Node name is '|SECOND:11|:462' 
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = LCELL( _EQ107);
  _EQ107 = !_LC2_A24 &  _LC3_A19 &  _LC4_A19
         #  _LC3_A19 &  _LC4_A19 & !_LC5_A19
         #  _LC2_A24 & !_LC3_A19 &  _LC4_A19 &  _LC5_A19;

-- Node name is '|SECOND:11|:468' 
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = LCELL( _EQ108);
  _EQ108 =  _LC2_A24 &  _LC4_A19 & !_LC5_A19
         # !_LC2_A24 &  _LC4_A19 &  _LC5_A19;

-- Node name is '|SECOND:11|:606' 
-- Equation name is '_LC4_A13', type is buried 
!_LC4_A13 = _LC4_A13~NOT;
_LC4_A13~NOT = LCELL( _EQ109);
  _EQ109 = !_LC8_A24
         # !EN
         # !_LC2_A19;



Project Information                               d:\zzr\eda\shizhong\shiz.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,056K

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