📄 shiz.rpt
字号:
- 7 - C 17 OR2 ! 0 4 0 1 |DECODER48:18|:33
- 6 - C 21 AND2 0 4 0 1 |DECODER48:18|:43
- 1 - C 13 OR2 s ! 0 2 0 1 |DECODER48:18|~171~1
- 4 - C 17 OR2 0 4 1 0 |DECODER48:18|:171
- 8 - C 21 OR2 0 4 0 1 |DECODER48:18|:190
- 1 - C 21 OR2 0 3 1 0 |DECODER48:18|:202
- 3 - C 21 OR2 s ! 0 4 0 2 |DECODER48:18|~204~1
- 6 - C 17 OR2 s ! 0 4 0 1 |DECODER48:18|~231~1
- 1 - C 17 OR2 0 4 1 0 |DECODER48:18|:235
- 3 - C 17 OR2 0 4 1 0 |DECODER48:18|:268
- 2 - C 17 OR2 0 4 1 0 |DECODER48:18|:301
- 4 - C 21 OR2 0 4 0 1 |DECODER48:18|:324
- 7 - C 21 OR2 0 4 1 0 |DECODER48:18|:334
- 8 - C 17 OR2 0 4 0 1 |DECODER48:18|:352
- 5 - C 21 OR2 0 4 1 0 |DECODER48:18|:367
- 7 - A 21 AND2 0 2 0 1 |HOUR:2|LPM_ADD_SUB:287|addcore:adder|:55
- 2 - A 21 AND2 0 3 0 1 |HOUR:2|LPM_ADD_SUB:287|addcore:adder|:59
- 1 - A 16 DFFE + 0 2 0 2 |HOUR:2|QH3 (|HOUR:2|:13)
- 3 - A 16 DFFE + 0 2 0 2 |HOUR:2|QH2 (|HOUR:2|:14)
- 5 - A 18 DFFE + 0 3 0 2 |HOUR:2|QH1 (|HOUR:2|:15)
- 4 - A 18 DFFE + 0 2 0 3 |HOUR:2|QH0 (|HOUR:2|:16)
- 1 - A 21 DFFE + 0 3 0 3 |HOUR:2|QL3 (|HOUR:2|:17)
- 8 - A 21 DFFE + 0 3 0 4 |HOUR:2|QL2 (|HOUR:2|:18)
- 3 - A 21 DFFE + 0 3 0 5 |HOUR:2|QL1 (|HOUR:2|:19)
- 5 - A 16 DFFE + 0 3 0 6 |HOUR:2|QL0 (|HOUR:2|:20)
- 8 - A 13 OR2 ! 1 2 0 8 |HOUR:2|:80
- 8 - A 16 AND2 ! 0 3 0 5 |HOUR:2|:95
- 4 - A 21 AND2 0 4 0 3 |HOUR:2|:116
- 5 - A 21 OR2 ! 0 4 0 6 |HOUR:2|:130
- 1 - A 18 AND2 0 3 0 1 |HOUR:2|:331
- 3 - A 18 OR2 0 4 0 1 |HOUR:2|:338
- 6 - A 21 OR2 s 0 3 0 1 |HOUR:2|~365~1
- 2 - A 18 AND2 s 0 2 0 3 |HOUR:2|~367~1
- 5 - A 20 AND2 0 2 0 1 |MINUTE:3|LPM_ADD_SUB:287|addcore:adder|:59
- 8 - A 14 AND2 0 2 0 1 |MINUTE:3|LPM_ADD_SUB:415|addcore:adder|:59
- 6 - A 14 AND2 0 3 0 1 |MINUTE:3|LPM_ADD_SUB:415|addcore:adder|:63
- 2 - A 20 DFFE + 0 3 0 3 |MINUTE:3|QN7 (|MINUTE:3|:14)
- 3 - A 20 DFFE + 0 3 0 4 |MINUTE:3|QN6 (|MINUTE:3|:15)
- 1 - A 20 DFFE + 0 3 0 5 |MINUTE:3|QN5 (|MINUTE:3|:16)
- 1 - A 15 DFFE + 0 2 0 5 |MINUTE:3|QN4 (|MINUTE:3|:17)
- 3 - A 14 DFFE + 0 3 0 2 |MINUTE:3|QN3 (|MINUTE:3|:18)
- 5 - A 14 DFFE + 0 3 0 3 |MINUTE:3|QN2 (|MINUTE:3|:19)
- 7 - A 14 DFFE + 0 3 0 4 |MINUTE:3|QN1 (|MINUTE:3|:20)
- 2 - A 14 DFFE + 0 1 0 5 |MINUTE:3|QN0 (|MINUTE:3|:21)
- 1 - A 13 OR2 1 2 0 8 |MINUTE:3|:89
- 1 - A 14 OR2 ! 0 4 0 9 |MINUTE:3|:115
- 4 - A 20 OR2 ! 0 4 0 2 |MINUTE:3|:185
- 2 - A 15 AND2 s 0 2 0 3 |MINUTE:3|~462~1
- 6 - A 20 OR2 0 4 0 1 |MINUTE:3|:462
- 8 - A 20 OR2 0 4 0 1 |MINUTE:3|:468
- 7 - A 20 OR2 0 3 0 1 |MINUTE:3|:474
- 5 - A 13 OR2 ! 0 3 0 1 |MINUTE:3|:612
- 8 - A 17 DFFE + 0 2 1 14 |MUX6:19|sel2 (|MUX6:19|:34)
- 1 - A 17 DFFE + 0 2 1 14 |MUX6:19|sel1 (|MUX6:19|:35)
- 7 - A 17 DFFE + 0 2 1 14 |MUX6:19|sel0 (|MUX6:19|:36)
- 5 - A 22 OR2 ! 0 4 0 1 |MUX6:19|:335
- 3 - A 22 OR2 ! 0 4 0 1 |MUX6:19|:336
- 4 - A 17 AND2 0 3 0 4 |MUX6:19|:341
- 6 - A 22 OR2 ! 0 4 0 1 |MUX6:19|:344
- 1 - A 22 OR2 ! 0 3 0 4 |MUX6:19|:351
- 7 - A 22 OR2 ! 0 3 0 1 |MUX6:19|:354
- 3 - A 17 OR2 ! 0 3 0 5 |MUX6:19|:361
- 8 - A 22 OR2 ! 0 3 0 1 |MUX6:19|:364
- 4 - A 22 OR2 ! 0 3 0 4 |MUX6:19|:371
- 2 - A 22 OR2 ! 0 3 0 13 |MUX6:19|:374
- 4 - A 16 AND2 0 4 0 1 |MUX6:19|:384
- 6 - A 16 AND2 0 4 0 1 |MUX6:19|:385
- 7 - A 16 OR2 0 4 0 1 |MUX6:19|:386
- 2 - A 16 OR2 0 3 0 1 |MUX6:19|:389
- 5 - A 23 OR2 0 3 0 1 |MUX6:19|:392
- 7 - A 23 OR2 0 3 0 13 |MUX6:19|:395
- 5 - A 17 AND2 0 4 0 1 |MUX6:19|:405
- 6 - A 17 AND2 0 4 0 1 |MUX6:19|:406
- 2 - A 17 OR2 0 4 0 1 |MUX6:19|:407
- 4 - A 14 OR2 0 3 0 1 |MUX6:19|:410
- 8 - A 23 OR2 0 3 0 1 |MUX6:19|:413
- 6 - A 23 OR2 0 3 0 13 |MUX6:19|:416
- 8 - A 18 AND2 0 4 0 1 |MUX6:19|:426
- 6 - A 18 AND2 0 4 0 1 |MUX6:19|:427
- 7 - A 18 OR2 0 4 0 1 |MUX6:19|:428
- 4 - A 23 AND2 0 2 0 1 |MUX6:19|:435
- 3 - A 23 OR2 0 4 0 1 |MUX6:19|:436
- 1 - A 23 OR2 0 4 0 13 |MUX6:19|:437
- 3 - A 11 DFFE + 1 1 0 2 |QUDOU:4|js1 (|QUDOU:4|:4)
- 1 - A 11 DFFE + 1 1 0 2 |QUDOU:4|js0 (|QUDOU:4|:5)
- 2 - A 11 DFFE + 1 2 0 1 |QUDOU:4|cp (|QUDOU:4|:6)
- 3 - A 13 DFFE + 1 1 0 2 |QUDOU:8|js1 (|QUDOU:8|:4)
- 2 - A 13 DFFE + 1 1 0 2 |QUDOU:8|js0 (|QUDOU:8|:5)
- 6 - A 13 DFFE + 1 2 0 1 |QUDOU:8|cp (|QUDOU:8|:6)
- 2 - A 23 AND2 0 2 0 1 |SECOND:11|LPM_ADD_SUB:281|addcore:adder|:59
- 7 - A 24 AND2 0 2 0 1 |SECOND:11|LPM_ADD_SUB:409|addcore:adder|:59
- 1 - A 24 OR2 0 4 0 1 |SECOND:11|LPM_ADD_SUB:409|addcore:adder|:77
- 1 - A 19 DFFE + 1 2 0 3 |SECOND:11|QN7 (|SECOND:11|:13)
- 3 - A 19 DFFE + 1 2 0 4 |SECOND:11|QN6 (|SECOND:11|:14)
- 5 - A 19 DFFE + 1 2 0 5 |SECOND:11|QN5 (|SECOND:11|:15)
- 2 - A 24 DFFE + 1 1 0 5 |SECOND:11|QN4 (|SECOND:11|:16)
- 5 - A 24 DFFE + 1 2 0 3 |SECOND:11|QN3 (|SECOND:11|:17)
- 4 - A 24 DFFE + 1 2 0 3 |SECOND:11|QN2 (|SECOND:11|:18)
- 6 - A 24 DFFE + 1 2 0 4 |SECOND:11|QN1 (|SECOND:11|:19)
- 3 - A 24 DFFE + 1 0 0 5 |SECOND:11|QN0 (|SECOND:11|:20)
- 8 - A 24 OR2 ! 0 4 0 9 |SECOND:11|:109
- 2 - A 19 OR2 ! 0 4 0 2 |SECOND:11|:179
- 4 - A 19 AND2 s 0 2 0 3 |SECOND:11|~456~1
- 6 - A 19 OR2 0 4 0 1 |SECOND:11|:456
- 8 - A 19 OR2 0 4 0 1 |SECOND:11|:462
- 7 - A 19 OR2 0 3 0 1 |SECOND:11|:468
- 4 - A 13 OR2 ! 1 2 0 2 |SECOND:11|:606
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\zzr\eda\shizhong\shiz.rpt
shiz
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 29/ 96( 30%) 0/ 48( 0%) 19/ 48( 39%) 2/16( 12%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 3/ 96( 3%) 0/ 48( 0%) 11/ 48( 22%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zzr\eda\shizhong\shiz.rpt
shiz
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 CP
INPUT 6 CLK
INPUT 3 CP1
Device-Specific Information: d:\zzr\eda\shizhong\shiz.rpt
shiz
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 27 RD
Device-Specific Information: d:\zzr\eda\shizhong\shiz.rpt
shiz
** EQUATIONS **
AH : INPUT;
AM : INPUT;
CLK : INPUT;
CP : INPUT;
CP1 : INPUT;
EN : INPUT;
MOD : INPUT;
RD : INPUT;
-- Node name is 'SEG0'
-- Equation name is 'SEG0', type is output
SEG0 = _LC5_C21;
-- Node name is 'SEG1'
-- Equation name is 'SEG1', type is output
SEG1 = _LC7_C21;
-- Node name is 'SEG2'
-- Equation name is 'SEG2', type is output
SEG2 = _LC2_C17;
-- Node name is 'SEG3'
-- Equation name is 'SEG3', type is output
SEG3 = _LC3_C17;
-- Node name is 'SEG4'
-- Equation name is 'SEG4', type is output
SEG4 = _LC1_C17;
-- Node name is 'SEG5'
-- Equation name is 'SEG5', type is output
SEG5 = _LC1_C21;
-- Node name is 'SEG6'
-- Equation name is 'SEG6', type is output
SEG6 = _LC4_C17;
-- Node name is 'SEG7'
-- Equation name is 'SEG7', type is output
SEG7 = GND;
-- Node name is 'SET0'
-- Equation name is 'SET0', type is output
SET0 = _LC7_A17;
-- Node name is 'SET1'
-- Equation name is 'SET1', type is output
SET1 = _LC1_A17;
-- Node name is 'SET2'
-- Equation name is 'SET2', type is output
SET2 = _LC8_A17;
-- Node name is '|DECODER48:18|:23'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = LCELL( _EQ001);
_EQ001 = !_LC1_A23 & !_LC2_A22 & !_LC6_A23 & !_LC7_A23;
-- Node name is '|DECODER48:18|:28'
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = LCELL( _EQ002);
_EQ002 = _LC1_A23 & !_LC2_A22 & !_LC6_A23 & !_LC7_A23;
-- Node name is '|DECODER48:18|:33'
-- Equation name is '_LC7_C17', type is buried
!_LC7_C17 = _LC7_C17~NOT;
_LC7_C17~NOT = LCELL( _EQ003);
_EQ003 = !_LC6_A23
# _LC2_A22
# _LC1_A23
# _LC7_A23;
-- Node name is '|DECODER48:18|:43'
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ004);
_EQ004 = !_LC1_A23 & !_LC2_A22 & !_LC6_A23 & _LC7_A23;
-- Node name is '|DECODER48:18|~171~1'
-- Equation name is '_LC1_C13', type is buried
-- synthesized logic cell
!_LC1_C13 = _LC1_C13~NOT;
_LC1_C13~NOT = LCELL( _EQ005);
_EQ005 = _LC5_C17
# _LC2_C21;
-- Node name is '|DECODER48:18|:171'
-- Equation name is '_LC4_C17', type is buried
_LC4_C17 = LCELL( _EQ006);
_EQ006 = !_LC1_A23 & !_LC2_A22 & _LC7_A23
# !_LC2_A22 & !_LC6_A23 & _LC7_A23
# !_LC1_A23 & !_LC2_A22 & _LC6_A23
# !_LC2_A22 & _LC6_A23 & !_LC7_A23
# _LC2_A22 & !_LC6_A23 & !_LC7_A23;
-- Node name is '|DECODER48:18|:190'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = LCELL( _EQ007);
_EQ007 = !_LC1_A23 & !_LC2_A22 & _LC7_A23
# !_LC2_A22 & !_LC6_A23 & _LC7_A23
# _LC2_A22 & !_LC6_A23 & !_LC7_A23;
-- Node name is '|DECODER48:18|:202'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ008);
_EQ008 = _LC3_C21 & _LC8_C21
# _LC2_C21;
-- Node name is '|DECODER48:18|~204~1'
-- Equation name is '_LC3_C21', type is buried
-- synthesized logic cell
!_LC3_C21 = _LC3_C21~NOT;
_LC3_C21~NOT = LCELL( _EQ009);
_EQ009 = !_LC2_A22 & _LC6_A23 & !_LC7_A23
# _LC1_A23 & !_LC2_A22 & !_LC7_A23;
-- Node name is '|DECODER48:18|~231~1'
-- Equation name is '_LC6_C17', type is buried
-- synthesized logic cell
!_LC6_C17 = _LC6_C17~NOT;
_LC6_C17~NOT = LCELL( _EQ010);
_EQ010 = !_LC1_A23 & !_LC2_A22 & !_LC6_A23 & _LC7_A23
# _LC1_A23 & !_LC2_A22 & _LC6_A23 & !_LC7_A23;
-- Node name is '|DECODER48:18|:235'
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = LCELL( _EQ011);
_EQ011 = !_LC1_A23 & !_LC2_A22 & !_LC7_A23
# !_LC1_A23 & !_LC2_A22 & _LC6_A23
# !_LC1_A23 & !_LC6_A23 & !_LC7_A23;
-- Node name is '|DECODER48:18|:268'
-- Equation name is '_LC3_C17', type is buried
_LC3_C17 = LCELL( _EQ012);
_EQ012 = !_LC1_A23 & !_LC2_A22 & !_LC7_A23
# !_LC2_A22 & _LC6_A23 & !_LC7_A23
# _LC1_A23 & !_LC2_A22 & !_LC6_A23 & _LC7_A23
# !_LC1_A23 & !_LC2_A22 & _LC6_A23
# !_LC1_A23 & !_LC6_A23 & !_LC7_A23;
-- Node name is '|DECODER48:18|:301'
-- Equation name is '_LC2_C17', type is buried
_LC2_C17 = LCELL( _EQ013);
_EQ013 = !_LC1_C13
# !_LC6_C17 & !_LC7_C17
# !_LC7_C17 & _LC8_C17;
-- Node name is '|DECODER48:18|:324'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = LCELL( _EQ014);
_EQ014 = _LC2_A22 & !_LC6_A23 & !_LC7_A23
# _LC1_A23 & !_LC2_A22 & _LC6_A23 & _LC7_A23;
-- Node name is '|DECODER48:18|:334'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = LCELL( _EQ015);
_EQ015 = !_LC3_C21
# _LC4_C21
# _LC2_C21
# _LC6_C21;
-- Node name is '|DECODER48:18|:352'
-- Equation name is '_LC8_C17', type is buried
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -