qudou.vhd

数字钟的VHDL源程序

library ieee;
use ieee.std_logic_1164.all;                        
use ieee.std_logic_unsigned.all;
entity qudou is
port(clk,key:in std_logic;
      cpo:out std_logic);
end qudou;
architecture str of qudou is
signal cp:std_logic;
signal js:integer range 0 to 3;
begin
process(clk,key)
begin 
if (clk'event and clk='1') then
  if key='1' then
    if js=3 then
     js<=js;
    else js<=js+1;
    end if;
   if js=3 then
   cp<='1';
   else cp<='0';
   end if;
   else
   js<=0;
   cp<='0';
    end if;
   end if;
end process;
cpo<=cp;
end str;