📄 hour.rpt
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Device-Specific Information: d:\zzr\eda\shizhong\hour.rpt
hour
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 9/ 96( 9%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zzr\eda\shizhong\hour.rpt
hour
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CP
Device-Specific Information: d:\zzr\eda\shizhong\hour.rpt
hour
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 RES
Device-Specific Information: d:\zzr\eda\shizhong\hour.rpt
hour
** EQUATIONS **
CP : INPUT;
EN : INPUT;
EN2 : INPUT;
RES : INPUT;
-- Node name is 'HH0'
-- Equation name is 'HH0', type is output
HH0 = QH0;
-- Node name is 'HH1'
-- Equation name is 'HH1', type is output
HH1 = QH1;
-- Node name is 'HH2'
-- Equation name is 'HH2', type is output
HH2 = QH2;
-- Node name is 'HH3'
-- Equation name is 'HH3', type is output
HH3 = QH3;
-- Node name is 'HL0'
-- Equation name is 'HL0', type is output
HL0 = QL0;
-- Node name is 'HL1'
-- Equation name is 'HL1', type is output
HL1 = QL1;
-- Node name is 'HL2'
-- Equation name is 'HL2', type is output
HL2 = QL2;
-- Node name is 'HL3'
-- Equation name is 'HL3', type is output
HL3 = QL3;
-- Node name is ':16' = 'QH0'
-- Equation name is 'QH0', location is LC1_B13, type is buried.
QH0 = DFFE( _EQ001, GLOBAL( CP), GLOBAL( RES), VCC, VCC);
_EQ001 = EN2 & _LC5_B13
# EN & _LC5_B13
# !EN & !EN2 & QH0;
-- Node name is ':15' = 'QH1'
-- Equation name is 'QH1', location is LC4_B13, type is buried.
QH1 = DFFE( _EQ002, GLOBAL( CP), GLOBAL( RES), VCC, VCC);
_EQ002 = _LC6_B13 & QH1
# _LC6_B17 & _LC8_B13;
-- Node name is ':14' = 'QH2'
-- Equation name is 'QH2', location is LC1_B21, type is buried.
QH2 = DFFE( _EQ003, GLOBAL( CP), GLOBAL( RES), VCC, VCC);
_EQ003 = !EN & !EN2 & QH2
# !_LC1_B17 & QH2;
-- Node name is ':13' = 'QH3'
-- Equation name is 'QH3', location is LC8_B21, type is buried.
QH3 = DFFE( _EQ004, GLOBAL( CP), GLOBAL( RES), VCC, VCC);
_EQ004 = !EN & !EN2 & QH3
# !_LC1_B17 & QH3;
-- Node name is ':20' = 'QL0'
-- Equation name is 'QL0', location is LC2_B17, type is buried.
QL0 = DFFE( _EQ005, GLOBAL( CP), GLOBAL( RES), VCC, VCC);
_EQ005 = !_LC1_B17 & _LC2_B13 & !QL0
# _LC2_B13 & !_LC4_B21 & !QL0
# !_LC2_B13 & QL0;
-- Node name is ':19' = 'QL1'
-- Equation name is 'QL1', location is LC3_B17, type is buried.
QL1 = DFFE( _EQ006, GLOBAL( CP), GLOBAL( RES), VCC, VCC);
_EQ006 = _LC7_B13 & !QL0 & QL1
# _LC2_B13 & _LC7_B13 & QL0 & !QL1
# !_LC2_B13 & QL1;
-- Node name is ':18' = 'QL2'
-- Equation name is 'QL2', location is LC7_B17, type is buried.
QL2 = DFFE( _EQ007, GLOBAL( CP), GLOBAL( RES), VCC, VCC);
_EQ007 = _LC3_B13 & !_LC4_B17 & QL2
# _LC3_B13 & _LC4_B17 & !QL2
# !_LC2_B13 & QL2;
-- Node name is ':17' = 'QL3'
-- Equation name is 'QL3', location is LC5_B17, type is buried.
QL3 = DFFE( _EQ008, GLOBAL( CP), GLOBAL( RES), VCC, VCC);
_EQ008 = _LC3_B13 & !_LC8_B17 & QL3
# _LC3_B13 & _LC8_B17 & !QL3
# !_LC2_B13 & QL3;
-- Node name is '|LPM_ADD_SUB:287|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B17', type is buried
_LC8_B17 = LCELL( _EQ009);
_EQ009 = QL0 & QL1 & QL2;
-- Node name is '~80~1'
-- Equation name is '~80~1', location is LC8_B13, type is buried.
-- synthesized logic cell
_LC8_B13 = LCELL( _EQ010);
_EQ010 = EN2 & !_LC4_B21 & QH0
# EN & !_LC4_B21 & QH0;
-- Node name is ':80'
-- Equation name is '_LC2_B13', type is buried
!_LC2_B13 = _LC2_B13~NOT;
_LC2_B13~NOT = LCELL( _EQ011);
_EQ011 = !EN & !EN2;
-- Node name is ':95'
-- Equation name is '_LC4_B21', type is buried
!_LC4_B21 = _LC4_B21~NOT;
_LC4_B21~NOT = LCELL( _EQ012);
_EQ012 = !QH1 & !QH2 & !QH3;
-- Node name is ':116'
-- Equation name is '_LC6_B17', type is buried
!_LC6_B17 = _LC6_B17~NOT;
_LC6_B17~NOT = LCELL( _EQ013);
_EQ013 = !QL3
# QL2
# QL1
# !QL0;
-- Node name is ':130'
-- Equation name is '_LC1_B17', type is buried
!_LC1_B17 = _LC1_B17~NOT;
_LC1_B17~NOT = LCELL( _EQ014);
_EQ014 = !QL1 & !QL2 & !QL3
# !QL0 & !QL2 & !QL3;
-- Node name is ':137'
-- Equation name is '_LC4_B17', type is buried
_LC4_B17 = LCELL( _EQ015);
_EQ015 = QL0 & QL1;
-- Node name is ':338'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ016);
_EQ016 = !_LC1_B17 & _LC4_B21 & QH0
# !_LC4_B21 & !_LC6_B17 & QH0
# !_LC4_B21 & _LC6_B17 & !QH0;
-- Node name is '~365~1'
-- Equation name is '~365~1', location is LC7_B13, type is buried.
-- synthesized logic cell
_LC7_B13 = LCELL( _EQ017);
_EQ017 = !_LC1_B17 & _LC4_B21
# !_LC4_B21 & !_LC6_B17;
-- Node name is '~406~1'
-- Equation name is '~406~1', location is LC6_B13, type is buried.
-- synthesized logic cell
_LC6_B13 = LCELL( _EQ018);
_EQ018 = !EN & !EN2
# !_LC1_B17;
-- Node name is '~419~1'
-- Equation name is '~419~1', location is LC3_B13, type is buried.
-- synthesized logic cell
_LC3_B13 = LCELL( _EQ019);
_EQ019 = _LC2_B13 & !_LC4_B21 & !_LC6_B17;
Project Information d:\zzr\eda\shizhong\hour.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,777K
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