addr.vhd

SDRAM基础性控制核 很有用的 VHDL状态机实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity addr iS
  port(
       ACLK   :in  std_logic;
       LEN    :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       ADDRESS:out std_logic_vector(21 downto 0);
       ADDR_FULL :OUT STD_LOGIC;
       RESET  :IN  STD_LOGIC;
       RESET_ADDR  :IN STD_LOGIC);
end addr;

architecture a_addr of addr is
SIGNAL ADDR:STD_LOGIC_VECTOR(12 DOWNTO 0);---(14 DOWNTO 0)
SIGNAL LENTH:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
-------------------------------------------------
PROCESS(RESET,RESET_ADDR,ACLK)
BEGIN
   IF RESET='0' OR RESET_ADDR='0' THEN
       ADDR<=(OTHERS=>'0');
	 
   ELSIF ACLK'EVENT AND ACLK='1' THEN
       ADDR<=ADDR+1;
      --ADDR(13 DOWNTO 12)<="00";
   END IF;
END PROCESS;
address(21 downto 20)<= "00";
ADDRESS(19 DOWNTO 8)<=ADDR(11 DOWNTO 0);
ADDRESS(7 DOWNTO 0)<=(OTHERS=>'0');
LENTH<="001" WHEN LEN="0011" ELSE     
       "010" WHEN LEN="0010" ELSE
       "011" WHEN LEN="0001" ELSE
       "100";


--ADDR_FULL<='1' WHEN LENTH=ADDR(14 DOWNTO 12) ELSE
ADDR_FULL<='1' WHEN ADDR(12)= '1' ELSE
       '0';
end a_addr;