we_rd.v

RAM读写控制器

module WE_RD(CLK50M,CLK40M,DCLK,VSYNC,HSYNC,BLANK,DATA_IN,YCLK_IN,QA_IN,QB_IN,
				wr_ab_addr,rd_ab_addr,wa_rb_en,wb_ra_en,
				wr_clk,rd_clk,data_a,data_b,Q_DATA);//wr_clken,rd_clken,

input 	 CLK50M,CLK40M,DCLK,VSYNC,HSYNC,BLANK,YCLK_IN;
input 	[3:0] DATA_IN,QA_IN,QB_IN;

output 	[3:0]data_a,data_b,Q_DATA;
output 	[11:0] wr_ab_addr,rd_ab_addr;
output  wa_rb_en,wb_ra_en,wr_clk,rd_clk;//wr_clken,rd_clken;

reg 	[3:0]data_a,data_b,Q_DATA;
reg     [11:0] wr_ab_addr,rd_ab_addr;

reg 	sig_vs1,sig_vs2;
reg 	sig_wrclken;
reg 	sig_rdclken;
reg 	[11:0] sig_wradd_cnt,sig_rdadd_cnt;
reg 	[10:0]sig_dat_vcnt;

wire 	sig_vsena,sig_vsenb;
wire 	rd_clk;
wire 	wr_clk;





//------------------------------------------------------------------rd_clk
always @(posedge CLK40M)//25NS
begin
   if(YCLK_IN==1'b1)
      sig_dat_vcnt<=sig_dat_vcnt+11'b00000000001;
   else
	  sig_dat_vcnt<=0;
end	

always @(posedge CLK40M)  
begin
	if(VSYNC==1'b0)
		sig_rdclken<=0;
	else
		if(VSYNC==1'b1)
			begin
			     if(sig_dat_vcnt<8||sig_dat_vcnt>39)
						sig_rdclken<=1'b0;
					else
						sig_rdclken<=1'b1;
                       end
		else
			sig_rdclken<=0;
end

assign rd_clk=sig_rdclken&(CLK40M); 
//------------------------------------------------------------------wr_clk

assign wr_clk=DCLK;

//------------------------------------------------------------------sig_rdadd_cnt
always @(posedge rd_clk)
begin
if(VSYNC==0)
	sig_rdadd_cnt<=0;
	else
		if(sig_rdclken==0)
			sig_rdadd_cnt<=sig_rdadd_cnt;
				else
					if(sig_rdclken==1)
						sig_rdadd_cnt<=sig_rdadd_cnt+12'b000000000001;
end


//------------------------------------------------------------------sig_wradd_cnt

always @(posedge wr_clk)
begin
if(VSYNC==0)
	sig_wradd_cnt<=0;
	else
		if(BLANK==0)
			sig_wradd_cnt<=sig_wradd_cnt;
				else
					if(BLANK==1)
						sig_wradd_cnt<=sig_wradd_cnt+12'b000000000001;
end

//------------------------------------------------------------------wr_ab_addr,rd_ab_addr

always @(posedge CLK50M)
begin
wr_ab_addr[11:0]<=sig_wradd_cnt[11:0];
rd_ab_addr[11:0]<=sig_rdadd_cnt[11:0];
end


//------------------------------------------------------------------wa_rb_en,wb_ra_en
always @(negedge VSYNC)
begin
	sig_vs1<=~sig_vs1;
end

always @(posedge VSYNC)
begin
	sig_vs2<=sig_vs1;
end

and (sig_vsena,sig_vs1,sig_vs2);
and (sig_vsenb,~sig_vs1,~sig_vs2);

assign wa_rb_en=sig_vsena;
assign wb_ra_en=sig_vsenb;



//------------------------------------------------------------------data_a,data_b
always @(posedge DCLK)
begin
if(sig_vsena==1)
	data_a[3:0]<=DATA_IN[3:0];
	else
	data_a[3:0]<=4'b1111;
end
always @(posedge CLK40M)
begin
	if(sig_vsenb==1)
			data_b[3:0]<=DATA_IN[3:0];
				else
				data_b[3:0]<=4'b1111;
end
//------------------------------------------------------------------QA_IN,QB_IN,Q_DATA

always @(posedge rd_clk)
begin
if(sig_vsena==1)
	Q_DATA[3:0]<=QB_IN[3:0];
	else
	if(sig_vsenb==1)
		Q_DATA[3:0]<=QA_IN[3:0];				
end







endmodule