read.v

用于FPGA实现单总线测温电阻DS18b20时序。在xilinx spartan 3中试过。

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:18:17 03/11/2008 
// Design Name: 
// Module Name:    READ 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DS18B20_PROC(start,sysclk,reset,dq,dq_ctl,temp_data,rdy);
input start,sysclk,reset;
input dq;
output dq_ctl,rdy;
output[15:0] temp_data;
//parameter memsize=8;
reg[63:0] zcm; //64位注册码存放区
reg[63:0] zcm_reg;
reg[15:0] temp;
reg[15:0] temp_reg; 
reg[31:0] t;
reg[7:0] wr_reg;
reg dq_ctl,rd_reg,rd_s,skip_f,init_f,wr_s,conv_f,match_f,snum_f,rs_f;
reg init_s,wr_skip,wr_convt,wr_match,wr_num,rd_convt,rd_temp,wr_zcm,rdy;
reg[6:0] state,next;
integer i,n;
wire rs;
parameter     INIT=7'b0000001, //
          SKIP_ROM=7'b0000010, //跳ROM
			   CONV_T=7'b0000100, //温度转换
			MATCH_ROM=7'b0001000, //匹配ROM
			 SEND_NUM=7'b0010000, //发送注册码
			READ_SAVE=7'b0100000, //读并保存结果 
          SEND_TEM=7'b1000000; //发送温度转换结果给DPJ.

always @(posedge rs or posedge sysclk)
 begin
  if(rs) state<=INIT;
  else   state<=next;
 end

always @(state or init_f or skip_f or conv_f or match_f or snum_f or rs_f )
begin 
 case(state)
        INIT:   if(!init_f)     next<=INIT;
	             else if(n==0)   next<=SKIP_ROM;
	    			 else				  next<=MATCH_ROM;
	 SKIP_ROM:   if(skip_f)      next<=CONV_T;
					 else            next<= SKIP_ROM;
	   CONV_T:   if(conv_f)      next<=INIT;                  
					 else            next<=CONV_T; 
	MATCH_ROM:   if(match_f)     next<=SEND_NUM;
	             else            next<=MATCH_ROM;
    SEND_NUM:   if(snum_f)      next<=READ_SAVE;
					 else            next<=SEND_NUM;
   READ_SAVE:   if(rs_f)        next<=SEND_TEM;
	             else            next<=READ_SAVE;
	 SEND_TEM:   				     next<= SEND_TEM;						 
  	default:                     next<=INIT;
	                             									  
  endcase
end


always @(posedge rs or posedge sysclk)
 begin
 if(rs)
 begin
	init_s<=0;
	wr_skip<=0;
	wr_convt<=0;
	wr_match<=0;
	wr_num<=0;
	t<=0;
	i<=0;
	dq_ctl<=1;
	rd_reg<=0;
	rd_convt<=0;
	rd_temp<=0;
 end
 //初始化DS18B20;
 else if((state==INIT)&&(init_f==0))
 begin
 case(t)  
 32'd0:   begin
          t<=t+1;
          dq_ctl<=0; 
			 end
 32'd600: begin
          t<=t+1;
          dq_ctl<=1; 
			 end        
 32'd1140:begin
          t<=0;
          if(dq==1)
       	 init_s<=1;
			 end
 default: if((t>680)&&(dq==1))
			 begin
			 wr_match<=0;
			 wr_num<=0;
			 rd_temp<=0;
			 rd_convt<=0;
			 init_s<=1;
			 t<=0;
			 end
			 else
			 t<=t+1;
 endcase
 end
//写8位字操作
 else if(wr_s==1)
	begin
		if(i<8)
		begin
			case(t)
			32'd0:  begin
						t<=t+1;
						dq_ctl<=0;
					  end
			32'd6:  begin
						t<=t+1;
						dq_ctl<=wr_reg[i];
					  end
			32'd62: begin
						dq_ctl<=1;
						t<=0;
						i<=i+1;
					  end
			default:t<=t+1;
			endcase
		end
		else
		begin
			i<=0;
			case(state)
			SKIP_ROM: wr_skip<=1;
			CONV_T:   wr_convt<=1;
			MATCH_ROM:wr_match<=1;
			default:  begin
							wr_skip<=0;
							wr_convt<=0;
							wr_match<=0;
						 end
			endcase  
		end
	end
  //写64
  else if(wr_zcm==1)
	  begin
	  if(i<64)
		  begin
		  case(t)
		  32'd0:  begin
					 t<=t+1;
					 dq_ctl<=0;
					 end
		  32'd6:  begin
					 t<=t+1;
					 dq_ctl<=zcm_reg[i];
					 end
		  32'd62: begin
					 dq_ctl<=1;
					 t<=0;
					 i<=i+1;
					 end
		  default:t<=t+1;
		  endcase
		  end
	  else
		  begin
		  i<=0;
		  wr_num<=1;
		  end
	  end
  
 //读转换是否完成
  else if((rd_s==1)&&(state==CONV_T))
  begin
  case(t)
  32'd0:  begin
          t<=t+1;
          dq_ctl<=0; 
			 end
  32'd6:  begin
          t<=t+1;
          dq_ctl<=1;
			 end
  32'd10: begin
          t<=t+1;
          rd_reg<=dq;
			 end
  32'd60: begin
          dq_ctl<=1;
          t<=0;
			 if(rd_reg==1)
			 rd_convt<=1;
			 init_s<=0;
			 end
  default:t<=t+1;			 
  endcase
  end
//读16位温度结果  
  else if((rd_s==1)&&(state==READ_SAVE))
  begin
  if(i<16)
	  begin
		  case(t)
		  32'd0:  begin
					 t<=t+1;
					 dq_ctl<=0; 
					 end
		  32'd6:  begin
					 t<=t+1;
					 dq_ctl<=1;
					 end
		  32'd10: begin 
					 t<=t+1; 
					 temp_reg[i]<=dq;
					 end
		  32'd60: begin
					 t<=0;
					 i<=i+1;
					 dq_ctl<=1;
					 end
		  default: t<=t+1; 
		  endcase

	  end
  else 
	  begin
	  i<=0;
	  rd_temp<=1;
	  end
  end
  end

always @(rs or rd_convt or rd_temp or state or wr_skip or wr_convt or wr_match or wr_num )
 if(rs)
 begin 
 n<=0;
 init_f<=0;
 skip_f<=0;
 conv_f<=0;
 match_f<=0;
 wr_zcm<=0;
 wr_reg<=8'h00;
 zcm_reg<=64'h0000000000000000;
 zcm<=64'h0000000000000000;
 rd_s<=0;
 rdy<=0;
 end
 else
 begin
  case(state)
 //初始化
 INIT:     begin
           if(init_s==0)
			  init_f<=0;
			  else
			  init_f<=1;
			  end
 //发送跳过ROM指令
 SKIP_ROM: begin
           if(wr_skip==0)
           begin
			  wr_reg<=8'hCC;
           wr_s<=1;
           end
			  else
			  begin
			  wr_s<=0;
			  skip_f<=1;
			  end
			  end
 //发送温度转换指令
 CONV_T:   begin
           if(wr_convt==0)    //?
				  begin
				  wr_reg<=8'h44;
				  wr_s<=1;
				  end
           else 
				  begin
				  wr_s<=0;
					  if(rd_convt==0)
						  rd_s<=1;
					  else 
						  begin
						  rd_s<=0;	
						  n<=1;
						  conv_f<=1;
						  end
				  end
			  end
			  
//发送匹配指令
 MATCH_ROM:begin
           if(wr_match==0)
           begin
			  wr_reg<=8'h55;
			  wr_s<=1;
			  end
			  else 
			  begin
			  wr_s<=0;
			  match_f<=1;
			  end
			  end
//发送相应
 SEND_NUM: begin
           if(wr_num==0)
			  begin
			  zcm_reg<=zcm;
			  wr_zcm<=1;
			  end
			  else
			  begin
			  wr_zcm<=0;
			  snum_f<=1;
           end			  
           end
//读并保存温度转换结果
 READ_SAVE:begin
           if(rd_temp<=0)
           rd_s<=1;
			  else
			  begin
//			  temp[n-1]<=temp_reg;
//			  n<=n+1;
			  temp<=temp_reg;
			  rs_f<=1;
			  end
			  end
//发送温度结果

  SEND_TEM:
			  begin
			  rdy<=1;
			  end
			  
		 
 endcase
 end
 assign temp_data = temp;
 
 assign rs=reset|start;
 
endmodule