iqit.v

a H.264/AVC Baseline Decoder

			IsLeftShift <= (QPc < 6)? 1'b0:1'b1;
				
	div6 div6 (
		.qp(QP),
		.div(QPdiv6)
		);
		
	always @ (residual_state or res_DC or QPdiv6)
		if (residual_state == `Intra16x16DCLevel_s) //Intra16x16DC
			case (QPdiv6)
				4'b0000:shift_len <= 2;	
				4'b0001:shift_len <= 1;	
				default:shift_len <= QPdiv6 - 2;
			endcase
		else if (res_DC)						//ChromaDC
			case (QPdiv6)
				4'b0000:shift_len <= 1;
				default:shift_len <= QPdiv6 - 1;
			endcase
		else                             //AC
			shift_len <= QPdiv6;
			
	rescale_shift rescale_shift0 (
		.IsLeftShift(IsLeftShift),
		.shift_input(product0),
		.shift_len(shift_len),
		.shift_output(shift_output0)
		);
	rescale_shift rescale_shift1 (
		.IsLeftShift(IsLeftShift),
		.shift_input(product1),
		.shift_len(shift_len),
		.shift_output(shift_output1)
		);
	rescale_shift rescale_shift2 (
		.IsLeftShift(IsLeftShift),
		.shift_input(product2),
		.shift_len(shift_len),
		.shift_output(shift_output2)
		);
	rescale_shift rescale_shift3 (
		.IsLeftShift(IsLeftShift),
		.shift_input(product3),
		.shift_len(shift_len),
		.shift_output(shift_output3)
		);
	//-----------------------------------------------------------------------
	//rounding 
	//-----------------------------------------------------------------------
	assign before_rounding0 = (rounding_counter != 0)? TwoD_output[0]:0;
	assign before_rounding1 = (rounding_counter != 0)? TwoD_output[1]:0;
	assign before_rounding2 = (rounding_counter != 0)? TwoD_output[2]:0;
	assign before_rounding3 = (rounding_counter != 0)? TwoD_output[3]:0;
							   
	assign rounding_sum0 = before_rounding0[14:5] + 1;
	assign rounding_sum1 = before_rounding1[14:5] + 1;
	assign rounding_sum2 = before_rounding2[14:5] + 1;
	assign rounding_sum3 = before_rounding3[14:5] + 1; 
	
	//-----------------------------------------------------------------------
	// Strore results 
	//-----------------------------------------------------------------------
	//1.	Store OneD_output
	integer	i;	
	always @ (posedge gclk_1D or negedge reset_n)
		if (reset_n == 0)
			for (i=0;i<16;i=i+1)
				OneD_output[i] <= 0;
		else if (OneD_counter != 0)
			case (OneD_counter)
				3'b100:
				begin
					OneD_output[0] <= butterfly_F0;OneD_output[1] <= butterfly_F1;
					OneD_output[2] <= butterfly_F2;OneD_output[3] <= butterfly_F3;
				end
				3'b011:
				begin
					OneD_output[4] <= butterfly_F0;OneD_output[5] <= butterfly_F1;
					OneD_output[6] <= butterfly_F2;OneD_output[7] <= butterfly_F3;
				end
				3'b010:
				begin
					OneD_output[8]  <= butterfly_F0;OneD_output[9]  <= butterfly_F1;
					OneD_output[10] <= butterfly_F2;OneD_output[11] <= butterfly_F3;
				end
				3'b001:
				begin
					OneD_output[12] <= butterfly_F0;OneD_output[13] <= butterfly_F1;
					OneD_output[14] <= butterfly_F2;OneD_output[15] <= butterfly_F3;
				end
			endcase
	
	//2.	Store TwoD_output
	integer	j;
	always @ (posedge gclk_2D or negedge reset_n)
		if (reset_n == 0)
			for (j=0;j<4;j=j+1)
				TwoD_output[j] <= 0;
		else if (TwoD_counter != 0)
		   begin
				TwoD_output[0] <= butterfly_F0; TwoD_output[1] <= butterfly_F1;
				TwoD_output[2] <= butterfly_F2; TwoD_output[3] <= butterfly_F3;
			end
		   			
	//3.1	Store rescale_output as DC_output
	integer m;
	always @ (posedge gclk_rescale or negedge reset_n)
		if (reset_n == 1'b0)
			for (m=0;m<16;m=m+1)
				DC_output[m] <= 0;
		else if (res_DC == 1'b1) 
			case (rescale_counter)
				3'b100:
				begin
					DC_output[0] <= shift_output0;	DC_output[2]  <= shift_output1;
					DC_output[8] <= shift_output2;	DC_output[10] <= shift_output3;
				end
				3'b011:
				begin
					DC_output[1] <= shift_output0;	DC_output[3]  <= shift_output1;
					DC_output[9] <= shift_output2;	DC_output[11] <= shift_output3;
				end
				3'b010:
				begin
					DC_output[4]  <= shift_output0;	DC_output[6]  <= shift_output1;
					DC_output[12] <= shift_output2;	DC_output[14] <= shift_output3;
				end
				3'b001:
				if (residual_state == `ChromaDCLevel_Cb_s)
				   begin
					   DC_output[0] <= shift_output0;	DC_output[1] <= shift_output1;
					   DC_output[2] <= shift_output2;	DC_output[3] <= shift_output3;
				   end
				else if (residual_state == `ChromaDCLevel_Cr_s)
				   begin
					   DC_output[4] <= shift_output0;	DC_output[5] <= shift_output1;
					   DC_output[6] <= shift_output2;	DC_output[7] <= shift_output3;
				   end  
				else       
				   begin
					   DC_output[5]  <= shift_output0;	DC_output[7]  <= shift_output1;
					   DC_output[13] <= shift_output2;	DC_output[15] <= shift_output3;
				   end
			endcase	  
			
	//3.2	Store rescale_output as AC_output
	integer	n;
	always @ (posedge gclk_rescale or negedge reset_n)
		if (reset_n == 1'b0)
			for (n=0;n<4;n=n+1)
				rescale_output[n] <= 0;
		else if (res_AC == 1'b1 && rescale_counter != 0)
		   begin
				rescale_output[0] <= shift_output0;	rescale_output[1] <= shift_output1;
				rescale_output[2] <= shift_output2;	rescale_output[3] <= shift_output3;
			end 
	
	//4.	Store rounding_output
	always @ (posedge gclk_rounding or negedge reset_n)
		if (reset_n == 1'b0)
			begin
				rounding_output_0  <= 0;rounding_output_1  <= 0;rounding_output_2  <= 0;rounding_output_3  <= 0;
				rounding_output_4  <= 0;rounding_output_5  <= 0;rounding_output_6  <= 0;rounding_output_7  <= 0;
				rounding_output_8  <= 0;rounding_output_9  <= 0;rounding_output_10 <= 0;rounding_output_11 <= 0;
				rounding_output_12 <= 0;rounding_output_13 <= 0;rounding_output_14 <= 0;rounding_output_15 <= 0;
			end
		else
			case (rounding_counter)
				3'b100:
				begin 
					rounding_output_0  <= rounding_sum0[9:1];
					rounding_output_4  <= rounding_sum1[9:1];
					rounding_output_8  <= rounding_sum2[9:1];
					rounding_output_12 <= rounding_sum3[9:1];
				end
				3'b011:
				begin 
					rounding_output_1  <= rounding_sum0[9:1];
					rounding_output_5  <= rounding_sum1[9:1];
					rounding_output_9  <= rounding_sum2[9:1];
					rounding_output_13 <= rounding_sum3[9:1];
				end
				3'b010:
				begin 
					rounding_output_2  <= rounding_sum0[9:1];
					rounding_output_6  <= rounding_sum1[9:1];
					rounding_output_10 <= rounding_sum2[9:1];
					rounding_output_14 <= rounding_sum3[9:1];
				end
				3'b001:
				begin 
					rounding_output_3  <= rounding_sum0[9:1];
					rounding_output_7  <= rounding_sum1[9:1];
					rounding_output_11 <= rounding_sum2[9:1];
					rounding_output_15 <= rounding_sum3[9:1];
				end
			endcase
	assign end_of_ACBlk4x4_IQIT = (rounding_counter == 3'b001)? 1'b1:1'b0;
	assign end_of_DCBlk_IQIT  = ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || 
                                residual_state == `ChromaDCLevel_Cr_s) && rescale_counter == 3'b001)? 1'b1:1'b0;
endmodule
	
module butterfly (D0,D1,D2,D3,F0,F1,F2,F3,IsHadamard);
	input [15:0] D0,D1,D2,D3;
	input IsHadamard;
	output [15:0] F0,F1,F2,F3;
	
	wire [15:0] T0,T1,T2,T3;
	wire [15:0] D1_scale,D3_scale;
	
	assign D1_scale = (IsHadamard == 1'b1)? D1:{D1[15],D1[15:1]};
	assign D3_scale = (IsHadamard == 1'b1)? D3:{D3[15],D3[15:1]};
	
	assign T0 = D0 + D2;
	assign T1 = D0 - D2;
	assign T2 = D1_scale - D3;
	assign T3 = D1 + D3_scale;
	
	assign F0 = T0 + T3;
	assign F1 = T1 + T2;
	assign F2 = T1 - T2;
	assign F3 = T0 - T3;
endmodule

module mod6 (qp,mod);
	input [5:0] qp;
	output [2:0] mod;
	reg [2:0] mod;
	always @ (qp)
		case (qp)
			0, 6,12,18,24,30,36,42,48:mod <= 3'b000;
			1, 7,13,19,25,31,37,43,49:mod <= 3'b001;
			2, 8,14,20,26,32,38,44,50:mod <= 3'b010;
			3, 9,15,21,27,33,39,45,51:mod <= 3'b011;
			4,10,16,22,28,34,40,46   :mod <= 3'b100;
			5,11,17,23,29,35,41,47   :mod <= 3'b101;
			default                  :mod <= 3'b000;
		endcase
endmodule

module div6 (qp,div);
	input [5:0] qp;
	output [3:0] div;
	reg [3:0] div;
	always @ (qp)
		case (qp)
			0, 1, 2, 3, 4, 5 :div <= 4'b0000;
			6, 7, 8, 9, 10,11:div <= 4'b0001;
			12,13,14,15,16,17:div <= 4'b0010;
			18,19,20,21,22,23:div <= 4'b0011;
			24,25,26,27,28,29:div <= 4'b0100;
			30,31,32,33,34,35:div <= 4'b0101;
			36,37,38,39,40,41:div <= 4'b0110;
			42,43,44,45,46,47:div <= 4'b0111;
			48,49,50,51      :div <= 4'b1000;
			default          :div <= 0;
		endcase
endmodule

module rescale_shift (IsLeftShift,shift_input,shift_len,shift_output);
	input IsLeftShift;
	input signed [15:0] shift_input;
	input [3:0] shift_len;
	output signed [15:0] shift_output;
	
	assign shift_output = (IsLeftShift == 1'b1)? (shift_input <<< shift_len):(shift_input >>> shift_len);
endmodule