📄 fub3.bde

📁 his design is a comparator that compares consecutive bits a0...a3 with b0...b3
💻 BDE
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SCHM0102

HEADER
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 VARIABLES
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  #ARCHITECTURE="Fub3"
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #ENTITY="Fub3"
  #LANGUAGE="VHDL"
  AUTHOR="ALDEC"
  COMPANY="ALDEC"
  CREATIONDATE="2/19/99"
  TITLE="Fub3"
 }
 SYMBOL "#default" "e_and2" "e_and2"
 {
  HEADER
  {
   VARIABLES
   {
    #FUB=""
    #HDL_ENTRIES="library STD;\\nuse STD.STANDARD;"
    #LANGUAGE="VHDL"
    #MODIFIED="943515636"
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     TEXT "$#NAME"
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     TEXT "$#NAME"
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    RECT  15, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     OUTLINE 0,2, (132,0,0)
     AREA (20,0,140,120)
     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in2"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "e_and3" "e_and3"
 {
  HEADER
  {
   VARIABLES
   {
    #HDL_ENTRIES="library IEEE;\\nuse ieee.std_logic_1164;"
    #LANGUAGE="VHDL"
    #MODIFIED="943515094"
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  }
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     TEXT "$#NAME"
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    TEXT  8, 0, 0
    {
     TEXT "$#NAME"
     RECT (95,29,134,53)
     ALIGN 6
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 7
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    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (24,69,51,93)
     ALIGN 4
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 10
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    TEXT  14, 0, 0
    {
     TEXT "$#NAME"
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     ALIGN 4
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     PARENT 13
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    }
    RECT  16, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     OUTLINE 0,2, (132,0,0)
     AREA (20,0,140,160)
     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in2"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  13, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in3"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "e_nor2" "e_nor2"
 {
  HEADER
  {
   VARIABLES
   {
    #FUB=""
    #HDL_ENTRIES="library STD;\\nuse STD.STANDARD;"
    #LANGUAGE="VHDL"
    #MODIFIED="943515496"
   }
  }
  PAGE "" 
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    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
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     ALIGN 4
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 4
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    }
    TEXT  8, 0, 0
    {
     TEXT "$#NAME"
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     ALIGN 6
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     TEXT "$#NAME"
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    RECT  19, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     OUTLINE 0,2, (132,0,0)
     AREA (20,0,140,120)
     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in2"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "e_not1" "e_not1"
 {
  HEADER
  {
   VARIABLES
   {
    #FUB=""
    #HDL_ENTRIES="library STD;\\nuse STD.STANDARD;"
    #LANGUAGE="VHDL"
    #MODIFIED="943515632"
   }
  }
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    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
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     ALIGN 4
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 4
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  8, 0, 0
    {
     TEXT "$#NAME"
     RECT (95,29,134,53)
     ALIGN 6
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 7
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    RECT  10, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     OUTLINE 0,2, (132,0,0)
     AREA (20,0,140,80)
     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
   }
  }
 }
}

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    #COMPONENT="Input"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
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    #SYMBOL="Input"
    #VHDL_TYPE=""
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   COORD (720,1120)
   VERTEXES ( (2,492) )
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   COORD (720,860)
   VERTEXES ( (2,494) )
  }
  TEXT  38, 0, 0
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   TEXT "$#REFERENCE"
   RECT (628,844,665,879)
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  NET WIRE  40, 0, 0
  INSTANCE  41, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="NET1327"
    #SYMBOL="Input"
    #VHDL_TYPE=""
   }
   COORD (720,340)
   ORIENTATION 3
   VERTEXES ( (2,523) )
  }
  TEXT  43, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (541,321,666,356)
   ALIGN 10
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 41
   FONT (12,0,0,400,0,0,0,"Arial")
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  INSTANCE  47, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="NET1320"
    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (1520,960)
   VERTEXES ( (2,497) )
  }
  TEXT  49, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1575,944,1700,979)
   MARGINS (1,1)
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  NET WIRE  51, 0, 0
  INSTANCE  52, 0, 0
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   VARIABLES
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    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="NET489"
    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (720,560)
   ORIENTATION 4
   VERTEXES ( (2,519) )
  }
  TEXT  54, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (556,541,665,576)
   ALIGN 10
   MARGINS (1,1)
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   PARENT 52
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  INSTANCE  55, 0, 0
  {
   VARIABLES
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    #COMPONENT="Output"
    #DOWNTO=""
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    #LIBRARY="#terminals"
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    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (1520,480)
   VERTEXES ( (2,525) )
  }
  TEXT  57, 0, 0
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   TEXT "$#REFERENCE"
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   VARIABLES
   {
    #COMPONENT="e_not1"
    #LIBRARY="#default"
    #REFERENCE="U0"
    #SYMBOL="e_not1"
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   COORD (780,1080)
   VERTEXES ( (4,516), (7,517) )
  }
  TEXT  61, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (780,1044,819,1079)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 58
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  62, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (780,1160,870,1195)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 58
   FONT (12,0,0,400,0,0,0,"Arial")
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  INSTANCE  63, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="e_not1"
    #LIBRARY="#default"
    #REFERENCE="U1"
    #SYMBOL="e_not1"
   }
   COORD (780,820)
   VERTEXES ( (4,498), (7,500) )
  }
  TEXT  66, 0, 0
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   TEXT "$#REFERENCE"
   RECT (780,784,819,819)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 63
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  TEXT  67, 0, 0
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   TEXT "$#COMPONENT"
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   MARGINS (1,1)
   COLOR (0,128,0)
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  NET WIRE  70, 0, 0
  INSTANCE  71, 0, 0
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   VARIABLES
   {
    #COMPONENT="e_and2"
    #LIBRARY="#default"
    #REFERENCE="U2"
    #SYMBOL="e_and2"
   }
   COORD (1060,1040)
   VERTEXES ( (4,502), (7,504), (10,505) )
  }
  TEXT  75, 0, 0
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   TEXT "$#REFERENCE"
   RECT (1060,1004,1099,1039)
   ALIGN 8
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   COLOR (0,0,192)
   PARENT 71
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  76, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1060,1161,1158,1196)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 71
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  79, 0, 0
  NET WIRE  81, 0, 0
  INSTANCE  82, 0, 0
  {
12 下一页
💿 文件大小 46 K
👤 上传用户 dante55
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#consecutive #comparator #compares #design
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