📄 fub0.bde

📁 his design is a comparator that compares consecutive bits a0...a3 with b0...b3
💻 BDE
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SCHM0102

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  #ARCHITECTURE="Fub0"
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #ENTITY="Fub0"
  #LANGUAGE="VHDL"
  AUTHOR="ALDEC"
  COMPANY="ALDEC"
  CREATIONDATE="2/19/99"
  TITLE="Fub0"
 }
 SYMBOL "#default" "e_and2" "e_and2"
 {
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    #FUB=""
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     OUTLINE 0,2, (132,0,0)
     AREA (20,0,140,120)
     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in2"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "e_and5" "e_and5"
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     VARIABLES
     {
      #OUTLINE_FILLING="1"
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     OUTLINE 0,2, (132,0,0)
     AREA (20,0,140,240)
     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in2"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  13, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in3"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  16, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in4"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  19, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in5"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "e_nor2" "e_nor2"
 {
  HEADER
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     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
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     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
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     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in2"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
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 SYMBOL "#default" "e_not1" "e_not1"
 {
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    PIN  4, 0, 0
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    PIN  7, 0, 0
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     COORD (160,40)
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     {
      #DIRECTION="OUT"
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     LINE  1, 0, 0
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      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
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12 下一页
💿 文件大小 46 K
👤 上传用户 dante55
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#consecutive #comparator #compares #design
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