sn7485_top.bde

his design is a comparator that compares consecutive bits a0...a3 with b0...b3

   NET 398
   VTX 1746, 1673
  }
  VTX  1749, 0, 0
  {
   COORD (1440,1360)
  }
  WIRE  1750, 0, 0
  {
   NET 390
   VTX 1674, 1749
  }
  VTX  1751, 0, 0
  {
   COORD (1780,1360)
  }
  WIRE  1752, 0, 0
  {
   NET 390
   VTX 1749, 1751
  }
  WIRE  1753, 0, 0
  {
   NET 390
   VTX 1751, 1675
  }
  WIRE  1754, 0, 0
  {
   NET 233
   VTX 1676, 1677
  }
  WIRE  1755, 0, 0
  {
   NET 237
   VTX 1678, 1679
  }
  WIRE  1756, 0, 0
  {
   NET 80
   VTX 1680, 1681
  }
  WIRE  1757, 0, 0
  {
   NET 84
   VTX 1682, 1683
  }
  WIRE  1758, 0, 0
  {
   NET 88
   VTX 1684, 1685
  }
  VTX  1764, 0, 0
  {
   COORD (1940,1580)
  }
  WIRE  1765, 0, 0
  {
   NET 1089
   VTX 1688, 1764
  }
  WIRE  1766, 0, 0
  {
   NET 1089
   VTX 1764, 1689
  }
  WIRE  1767, 0, 0
  {
   NET 519
   VTX 1690, 1691
  }
  VTX  1768, 0, 0
  {
   COORD (1980,1620)
  }
  WIRE  1769, 0, 0
  {
   NET 1095
   VTX 1692, 1768
  }
  WIRE  1770, 0, 0
  {
   NET 1095
   VTX 1768, 1693
  }
  VTX  1771, 0, 0
  {
   COORD (1600,1260)
  }
  WIRE  1772, 0, 0
  {
   NET 1299
   VTX 1694, 1771
  }
  WIRE  1773, 0, 0
  {
   NET 1299
   VTX 1771, 1695
  }
  VTX  1774, 0, 0
  {
   COORD (1600,1700)
  }
  WIRE  1775, 0, 0
  {
   NET 1299
   VTX 1695, 1774
  }
  WIRE  1776, 0, 0
  {
   NET 1299
   VTX 1774, 1696
  }
  VTX  1777, 0, 0
  {
   COORD (1620,940)
  }
  WIRE  1778, 0, 0
  {
   NET 1320
   VTX 1697, 1777
  }
  WIRE  1779, 0, 0
  {
   NET 1320
   VTX 1777, 1698
  }
  VTX  1780, 0, 0
  {
   COORD (1620,1660)
  }
  WIRE  1781, 0, 0
  {
   NET 1320
   VTX 1699, 1780
  }
  WIRE  1782, 0, 0
  {
   NET 1320
   VTX 1780, 1700
  }
  VTX  1783, 0, 0
  {
   COORD (1660,620)
  }
  WIRE  1784, 0, 0
  {
   NET 1327
   VTX 1701, 1783
  }
  WIRE  1785, 0, 0
  {
   NET 1327
   VTX 1783, 1702
  }
  VTX  1786, 0, 0
  {
   COORD (1660,1620)
  }
  WIRE  1787, 0, 0
  {
   NET 1327
   VTX 1703, 1786
  }
  WIRE  1788, 0, 0
  {
   NET 1327
   VTX 1786, 1704
  }
  WIRE  1789, 0, 0
  {
   NET 1320
   VTX 1698, 1705
  }
  WIRE  1790, 0, 0
  {
   NET 1327
   VTX 1706, 1707
  }
  WIRE  1791, 0, 0
  {
   NET 1327
   VTX 1702, 1706
  }
  WIRE  1792, 0, 0
  {
   NET 1327
   VTX 1702, 1708
  }
  WIRE  1804, 0, 0
  {
   NET 1320
   VTX 1698, 1699
  }
  WIRE  1806, 0, 0
  {
   NET 1327
   VTX 1706, 1703
  }
  INSTANCE  1982, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Fub4"
    #LIBRARY="#default"
    #REFERENCE="U4"
    #SYMBOL="Fub4"
   }
   COORD (1240,480)
   VERTEXES ( (3,1659), (8,1657), (18,1664), (26,1666), (31,1701) )
  }
  TEXT  1983, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1240,700,1308,735)
   MARGINS (1,1)
   PARENT 1982
  }
  TEXT  1987, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1240,444,1279,479)
   ALIGN 8
   MARGINS (1,1)
   PARENT 1982
  }
  INSTANCE  2019, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Fub3"
    #LIBRARY="#default"
    #REFERENCE="U3"
    #SYMBOL="Fub3"
   }
   COORD (1240,800)
   VERTEXES ( (3,1655), (6,1653), (16,1708), (21,1697), (31,1668), (36,1670) )
  }
  TEXT  2020, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1240,1020,1308,1055)
   MARGINS (1,1)
   PARENT 2019
  }
  TEXT  2024, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1240,764,1279,799)
   ALIGN 8
   MARGINS (1,1)
   PARENT 2019
  }
  INSTANCE  2056, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Fub2"
    #LIBRARY="#default"
    #REFERENCE="U2"
    #SYMBOL="Fub2"
   }
   COORD (1240,1120)
   VERTEXES ( (3,1651), (8,1649), (13,1705), (18,1707), (21,1694), (26,1672), (31,1674) )
  }
  TEXT  2057, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1240,1340,1308,1375)
   MARGINS (1,1)
   PARENT 2056
  }
  TEXT  2061, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1240,1084,1279,1119)
   ALIGN 8
   MARGINS (1,1)
   PARENT 2056
  }
  INSTANCE  2093, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Fub0"
    #LIBRARY="#default"
    #REFERENCE="U0"
    #SYMBOL="Fub0"
   }
   COORD (1240,1500)
   VERTEXES ( (3,2286), (8,2288), (33,2295), (38,2297), (13,2289), (18,2290), (23,2291), (28,2323) )
  }
  TEXT  2094, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1240,1720,1308,1755)
   MARGINS (1,1)
   PARENT 2093
  }
  TEXT  2098, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1240,1464,1279,1499)
   ALIGN 8
   MARGINS (1,1)
   PARENT 2093
  }
  INSTANCE  2130, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Fub1"
    #LIBRARY="#default"
    #REFERENCE="U1"
    #SYMBOL="Fub1"
   }
   COORD (1700,1540)
   VERTEXES ( (3,1688), (8,1692), (13,1704), (18,1700), (23,1696), (33,1685), (38,1683), (43,1681), (48,1690), (28,2322) )
  }
  TEXT  2131, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1700,1940,1768,1975)
   MARGINS (1,1)
   PARENT 2130
  }
  TEXT  2135, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1700,1504,1739,1539)
   ALIGN 8
   MARGINS (1,1)
   PARENT 2130
  }
  INSTANCE  2167, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Fub5"
    #LIBRARY="#default"
    #REFERENCE="U5"
    #SYMBOL="Fub5"
   }
   COORD (1740,860)
   VERTEXES ( (3,1671), (8,1669), (13,1667), (18,1665), (23,1675), (26,1673), (41,1689), (46,1693), (51,1678), (56,1676), (31,2294), (36,2296) )
  }
  TEXT  2168, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1740,1260,1808,1295)
   MARGINS (1,1)
   PARENT 2167
  }
  TEXT  2172, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1740,824,1779,859)
   ALIGN 8
   MARGINS (1,1)
   PARENT 2167
  }
  VTX  2285, 0, 0
  {
   COORD (1180,1580)
  }
  VTX  2286, 0, 0
  {
   COORD (1240,1580)
  }
  VTX  2287, 0, 0
  {
   COORD (1180,1640)
  }
  VTX  2288, 0, 0
  {
   COORD (1240,1640)
  }
  VTX  2289, 0, 0
  {
   COORD (1540,1520)
  }
  VTX  2290, 0, 0
  {
   COORD (1540,1560)
  }
  VTX  2291, 0, 0
  {
   COORD (1540,1600)
  }
  VTX  2294, 0, 0
  {
   COORD (1860,1260)
  }
  VTX  2295, 0, 0
  {
   COORD (1320,1500)
  }
  VTX  2296, 0, 0
  {
   COORD (1900,1260)
  }
  VTX  2297, 0, 0
  {
   COORD (1440,1500)
  }
  WIRE  2298, 0, 0
  {
   NET 41
   VTX 2285, 2286
  }
  WIRE  2299, 0, 0
  {
   NET 37
   VTX 2287, 2288
  }
  WIRE  2300, 0, 0
  {
   NET 1327
   VTX 1703, 2289
  }
  WIRE  2301, 0, 0
  {
   NET 1320
   VTX 1699, 2290
  }
  WIRE  2302, 0, 0
  {
   NET 1299
   VTX 1695, 2291
  }
  VTX  2312, 0, 0
  {
   COORD (1860,1460)
  }
  WIRE  2313, 0, 0
  {
   NET 536
   VTX 2294, 2312
  }
  VTX  2314, 0, 0
  {
   COORD (1320,1460)
  }
  WIRE  2315, 0, 0
  {
   NET 536
   VTX 2312, 2314
  }
  WIRE  2316, 0, 0
  {
   NET 536
   VTX 2314, 2295
  }
  VTX  2317, 0, 0
  {
   COORD (1900,1480)
  }
  WIRE  2318, 0, 0
  {
   NET 544
   VTX 2296, 2317
  }
  VTX  2319, 0, 0
  {
   COORD (1440,1480)
  }
  WIRE  2320, 0, 0
  {
   NET 544
   VTX 2317, 2319
  }
  WIRE  2321, 0, 0
  {
   NET 544
   VTX 2319, 2297
  }
  VTX  2322, 0, 0
  {
   COORD (1700,1740)
  }
  VTX  2323, 0, 0
  {
   COORD (1540,1640)
  }
  VTX  2324, 0, 0
  {
   COORD (1580,1740)
  }
  WIRE  2325, 0, 0
  {
   NET 294
   VTX 2322, 2324
  }
  VTX  2326, 0, 0
  {
   COORD (1580,1640)
  }
  WIRE  2327, 0, 0
  {
   NET 294
   VTX 2324, 2326
  }
  WIRE  2328, 0, 0
  {
   NET 294
   VTX 2326, 2323
  }
 }
 
}

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"(C)ALDEC. Inc\n"+
"2260 Corporate Circle\n"+
"Henderson, NV 89074"
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   TEXT "The Design Verification Company"
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