sn7485_top.bde

his design is a comparator that compares consecutive bits a0...a3 with b0...b3

SCHM0102

HEADER
{
 FREEID 2385
 VARIABLES
 {
  #ARCHITECTURE="SN7485_TOP"
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #ENTITY="SN7485_TOP"
  #LANGUAGE="VHDL"
  AUTHOR="ALDEC"
  COMPANY="ALDEC"
  CREATIONDATE="2/19/99"
  TITLE="SN7485_TOP"
 }
 SYMBOL "#default" "Fub0" "Fub0"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VHDL"
    #MODIFIED="1002115343"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,300,220)
    FREEID 40
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (0,0,300,220)
    }
    TEXT  4, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,68,40,92)
     ALIGN 4
     MARGINS (1,1)
     PARENT 3
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,128,40,152)
     ALIGN 4
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  14, 0, 0
    {
     TEXT "$#NAME"
     RECT (203,8,287,32)
     ALIGN 6
     MARGINS (1,1)
     PARENT 13
    }
    TEXT  19, 0, 0
    {
     TEXT "$#NAME"
     RECT (203,48,287,72)
     ALIGN 6
     MARGINS (1,1)
     PARENT 18
    }
    TEXT  24, 0, 0
    {
     TEXT "$#NAME"
     RECT (203,88,287,112)
     ALIGN 6
     MARGINS (1,1)
     PARENT 23
    }
    TEXT  29, 0, 0
    {
     TEXT "$#NAME"
     RECT (214,128,287,152)
     ALIGN 6
     MARGINS (1,1)
     PARENT 28
    }
    TEXT  34, 0, 0
    {
     TEXT "$#NAME"
     RECT (68,14,92,87)
     ALIGN 1
     MARGINS (1,1)
     PARENT 33
     ORIENTATION 5
    }
    TEXT  39, 0, 0
    {
     TEXT "$#NAME"
     RECT (188,14,212,87)
     ALIGN 1
     MARGINS (1,1)
     PARENT 38
     ORIENTATION 5
    }
    PIN  3, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="B0"
      #NUMBER="1"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  8, 0, 0
    {
     COORD (0,140)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="A0"
      #NUMBER="2"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  13, 0, 0
    {
     COORD (300,20)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="NET1327"
      #NUMBER="3"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  18, 0, 0
    {
     COORD (300,60)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="NET1320"
      #NUMBER="4"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  23, 0, 0
    {
     COORD (300,100)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="NET1299"
      #NUMBER="5"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  28, 0, 0
    {
     COORD (300,140)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LABEL="Out"
      #MODIFIED="1"
      #NAME="NET294"
      #NUMBER="6"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  33, 0, 0
    {
     COORD (80,0)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LABEL="Out"
      #MODIFIED="1"
      #NAME="NET536"
      #NUMBER="7"
      #SIDE="top"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,0), (10,10), (-10,10), (0,0) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  38, 0, 0
    {
     COORD (200,0)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LABEL="Out"
      #MODIFIED="1"
      #NAME="NET544"
      #NUMBER="8"
      #SIDE="top"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,0), (10,10), (-10,10), (0,0) )
      FILL (0,(0,0,0),0)
     }
    }
   }
  }
 }
 SYMBOL "#default" "Fub1" "Fub1"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VHDL"
    #MODIFIED="1002115624"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,200,400)
    FREEID 50
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (0,0,200,400)
    }
    TEXT  4, 0, 0
    {
     TEXT "$#NAME"
     RECT (103,28,187,52)
     ALIGN 6
     MARGINS (1,1)
     PARENT 3
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (103,68,187,92)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  14, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,68,98,92)
     ALIGN 4
     MARGINS (1,1)
     PARENT 13
    }
    TEXT  19, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,108,98,132)
     ALIGN 4
     MARGINS (1,1)
     PARENT 18
    }
    TEXT  24, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,148,98,172)
     ALIGN 4
     MARGINS (1,1)
     PARENT 23
    }
    TEXT  29, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,188,87,212)
     ALIGN 4
     MARGINS (1,1)
     PARENT 28
    }
    TEXT  34, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,228,38,252)
     ALIGN 4
     MARGINS (1,1)
     PARENT 33
    }
    TEXT  39, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,268,42,292)
     ALIGN 4
     MARGINS (1,1)
     PARENT 38
    }
    TEXT  44, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,308,40,332)
     ALIGN 4
     MARGINS (1,1)
     PARENT 43
    }
    TEXT  49, 0, 0
    {
     TEXT "$#NAME"
     RECT (170,188,187,212)
     ALIGN 6
     MARGINS (1,1)
     PARENT 48
    }
    PIN  3, 0, 0
    {
     COORD (200,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LABEL="Out"
      #MODIFIED="1"
      #NAME="NET1089"
      #NUMBER="1"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  8, 0, 0
    {
     COORD (200,80)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LABEL="Out"
      #MODIFIED="1"
      #NAME="NET1095"
      #NUMBER="2"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  13, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="NET1327"
      #NUMBER="3"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  18, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="NET1320"
      #NUMBER="4"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  23, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="NET1299"
      #NUMBER="5"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  28, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="NET294"
      #NUMBER="6"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  33, 0, 0
    {
     COORD (0,240)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="L0"
      #NUMBER="7"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  38, 0, 0
    {
     COORD (0,280)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="M0"
      #NUMBER="8"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  43, 0, 0
    {
     COORD (0,320)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="K0"
      #NUMBER="9"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  48, 0, 0
    {
     COORD (200,200)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LABEL="Out"
      #MODIFIED="1"
      #NAME="M"
      #NUMBER="10"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
      FILL (0,(0,0,0),0)
     }
    }
   }
  }
 }
 SYMBOL "#default" "Fub2" "Fub2"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VHDL"
    #MODIFIED="1002114537"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,300,220)
    FREEID 33
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (0,0,300,220)
    }
    TEXT  4, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,68,40,92)
     ALIGN 4
     MARGINS (1,1)
     PARENT 3
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (14,128,40,152)
     ALIGN 4
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  14, 0, 0
    {
     TEXT "$#NAME"
     RECT (203,68,287,92)
     ALIGN 6
     MARGINS (1,1)
     PARENT 13
    }
    TEXT  19, 0, 0
    {
     TEXT "$#NAME"
     RECT (203,28,287,52)
     ALIGN 6
     MARGINS (1,1)
     PARENT 18
    }
    TEXT  22, 0, 0
    {
     TEXT "$#NAME"
     RECT (203,128,287,152)
     ALIGN 6
     MARGINS (1,1)
     PARENT 21
    }
    TEXT  27, 0, 0
    {
     TEXT "$#NAME"
     RECT (68,134,92,207)
     ALIGN 9
     MARGINS (1,1)
     PARENT 26
     ORIENTATION 5
    }
    TEXT  32, 0, 0
    {
     TEXT "$#NAME"
     RECT (188,134,212,207)
     ALIGN 9
     MARGINS (1,1)
     PARENT 31
     ORIENTATION 5
    }
    PIN  3, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="B1"
      #NUMBER="1"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  8, 0, 0
    {
     COORD (0,140)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="A1"
      #NUMBER="2"
      #SIDE="left"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  13, 0, 0
    {
     COORD (300,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="NET1320"
      #NUMBER="3"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  18, 0, 0
    {
     COORD (300,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="In"
      #MODIFIED="1"
      #NAME="NET1327"
      #NUMBER="4"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  21, 0, 0
    {
     COORD (300,140)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LABEL="Out"
      #MODIFIED="1"
      #NAME="NET1299"
      #NUMBER="5"
      #SIDE="right"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
      FILL (0,(0,0,0),0)
     }
    }
    PIN  26, 0, 0
    {