📄 fub4.bde

📁 his design is a comparator that compares consecutive bits a0...a3 with b0...b3
💻 BDE
📖 第 1 页 / 共 2 页
字号:
12 下一页
SCHM0102

HEADER
{
 FREEID 613
 VARIABLES
 {
  #ARCHITECTURE="Fub4"
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #ENTITY="Fub4"
  #LANGUAGE="VHDL"
  AUTHOR="ALDEC"
  COMPANY="ALDEC"
  CREATIONDATE="2/19/99"
  TITLE="Fub4"
 }
 SYMBOL "#default" "e_and2" "e_and2"
 {
  HEADER
  {
   VARIABLES
   {
    #FUB=""
    #HDL_ENTRIES="library STD;\\nuse STD.STANDARD;"
    #LANGUAGE="VHDL"
    #MODIFIED="943515636"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,160,120)
    FREEID 16
   }
   
   BODY
   {
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (24,29,51,53)
     ALIGN 4
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 4
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  8, 0, 0
    {
     TEXT "$#NAME"
     RECT (95,29,134,53)
     ALIGN 6
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 7
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (24,69,51,93)
     ALIGN 4
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 10
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    RECT  15, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     OUTLINE 0,2, (132,0,0)
     AREA (20,0,140,120)
     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in2"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "e_nor2" "e_nor2"
 {
  HEADER
  {
   VARIABLES
   {
    #FUB=""
    #HDL_ENTRIES="library STD;\\nuse STD.STANDARD;"
    #LANGUAGE="VHDL"
    #MODIFIED="943515496"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,160,120)
    FREEID 20
   }
   
   BODY
   {
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (24,29,51,53)
     ALIGN 4
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 4
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  8, 0, 0
    {
     TEXT "$#NAME"
     RECT (95,29,134,53)
     ALIGN 6
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 7
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (24,69,51,93)
     ALIGN 4
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 10
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    RECT  19, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     OUTLINE 0,2, (132,0,0)
     AREA (20,0,140,120)
     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in2"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "e_not1" "e_not1"
 {
  HEADER
  {
   VARIABLES
   {
    #FUB=""
    #HDL_ENTRIES="library STD;\\nuse STD.STANDARD;"
    #LANGUAGE="VHDL"
    #MODIFIED="943515632"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,160,80)
    FREEID 11
   }
   
   BODY
   {
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (24,29,51,53)
     ALIGN 4
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 4
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  8, 0, 0
    {
     TEXT "$#NAME"
     RECT (95,29,134,53)
     ALIGN 6
     MARGINS (1,1)
     COLOR (0,0,192)
     PARENT 7
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    RECT  10, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     OUTLINE 0,2, (132,0,0)
     AREA (20,0,140,80)
     FILL (0,(255,255,180),0)
    }
    PIN  4, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="in1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  7, 0, 0
    {
     COORD (160,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO=""
      #INITIAL_VALUE=""
      #LENGTH="20"
      #NAME="out1"
      #NUMBER="0"
      #VHDL_TYPE="std_logic"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (64,92,92)
      POINTS ( (-20,0), (0,0) )
     }
    }
   }
  }
 }
}

PAGE ""
{
 PAGEHEADER
 {
  PAGESIZE (2200,1700)
  MARGINS (200,200,200,200)
  RECT (0,0,0,0)
 }
 
 BODY
 {
  INSTANCE  26, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="A3"
    #SYMBOL="Input"
    #VHDL_TYPE=""
   }
   COORD (700,1060)
   VERTEXES ( (2,506) )
  }
  TEXT  28, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (608,1044,645,1079)
   ALIGN 2
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 26
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  31, 0, 0
  INSTANCE  41, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="B3"
    #SYMBOL="Input"
    #VHDL_TYPE=""
   }
   COORD (700,800)
   VERTEXES ( (2,512) )
  }
  TEXT  43, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (608,784,645,819)
   ALIGN 2
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 41
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  45, 0, 0
  INSTANCE  58, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="NET1327"
    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (1500,900)
   VERTEXES ( (2,519) )
  }
  TEXT  60, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1555,884,1680,919)
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 58
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  62, 0, 0
  INSTANCE  64, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="NET505"
    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (700,500)
   ORIENTATION 4
   VERTEXES ( (2,521) )
  }
  TEXT  66, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (536,481,645,516)
   ALIGN 10
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 64
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  68, 0, 0
  INSTANCE  69, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="NET497"
    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (1500,460)
   VERTEXES ( (2,535) )
  }
  TEXT  71, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1555,444,1664,479)
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 69
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  INSTANCE  72, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="e_not1"
    #LIBRARY="#default"
    #REFERENCE="U0"
    #SYMBOL="e_not1"
   }
   COORD (760,1020)
   VERTEXES ( (4,511), (7,523) )
  }
  TEXT  75, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (760,984,799,1019)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 72
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  76, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (760,1100,850,1135)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 72
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  78, 0, 0
  INSTANCE  79, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="e_not1"
    #LIBRARY="#default"
    #REFERENCE="U1"
    #SYMBOL="e_not1"
   }
   COORD (760,760)
   VERTEXES ( (4,514), (7,525) )
  }
  TEXT  82, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (760,724,799,759)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 79
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  83, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (760,841,850,876)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 79
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  85, 0, 0
  INSTANCE  90, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="e_and2"
    #LIBRARY="#default"
    #REFERENCE="U2"
    #SYMBOL="e_and2"
   }
   COORD (1040,980)
   VERTEXES ( (4,516), (7,529), (10,530) )
  }
  TEXT  94, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1040,944,1079,979)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 90
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  95, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1040,1101,1138,1136)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 90
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  97, 0, 0
  INSTANCE  106, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="e_and2"
    #LIBRARY="#default"
    #REFERENCE="U3"
    #SYMBOL="e_and2"
   }
   COORD (1080,760)
   VERTEXES ( (4,526), (7,532), (10,508) )
  }
  TEXT  110, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1080,724,1119,759)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 106
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  111, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1080,881,1178,916)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 106
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  113, 0, 0
  INSTANCE  133, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="e_nor2"
    #LIBRARY="#default"
    #REFERENCE="U6"
    #SYMBOL="e_nor2"
   }
   COORD (1300,860)
   VERTEXES ( (4,533), (7,518), (10,528) )
  }
  TEXT  136, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1300,824,1339,859)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 133
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  137, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1300,981,1392,1016)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 133
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  147, 0, 0
  INSTANCE  247, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="e_and2"
12 下一页
💿 文件大小 46 K
👤 上传用户 dante55
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#consecutive #comparator #compares #design
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -