processor_top.vo

PROCESSOR is a design with simple microprocessor implementation.

// Copyright (C) 1991-2003 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 2.2 Build 191 03/31/2003 Service Pack 2 SJ Full Version"

// DATE "09/30/2003 10:43:10"

//
// Device: Altera EP20K30EQC208-1 Package PQFP208
// 

// 
// This Verilog file should be used for CUSTOM VERILOG HDL only
// 

`timescale 1 ps/ 1 ps

module 	processor_top (
	rst,
	inp,
	P1,
	outp);
input 	rst;
input 	[31:0] inp;
input 	P1;
output 	[31:0] outp;

supply0 gnd;
supply1 vcc;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
// initial $sdf_annotate("processor_top_v.sdo");
// synopsys translate_on

wire N_1;
wire N_2;
wire N_3;
wire N_4;
wire N_5;
wire N_6;
wire N_7;
wire N_8;
wire N_9;
wire N_10;
wire N_11;
wire N_12;
wire N_13;
wire N_14;
wire N_15;
wire N_16;
wire N_17;
wire N_18;
wire N_19;
wire N_20;
wire N_21;
wire N_22;
wire N_23;
wire N_24;
wire N_25;
wire N_26;
wire N_27;
wire N_28;
wire N_29;
wire N_30;
wire \Instance0|Instance0|N_1 ;
wire \Instance0|Instance0|N_2 ;
wire \Instance0|Instance0|N_3 ;
wire \Instance0|Instance0|N_4 ;
wire \Instance0|Instance0|N_5 ;
wire \Instance0|Instance0|N_6 ;
wire \Instance0|Instance0|N_7 ;
wire \rst~padio ;
wire \outp[31]~padio ;
wire \outp[30]~padio ;
wire \outp[29]~padio ;
wire \outp[28]~padio ;
wire \outp[27]~padio ;
wire \outp[26]~padio ;
wire \outp[25]~padio ;
wire \outp[24]~padio ;
wire \outp[23]~padio ;
wire \outp[22]~padio ;
wire \outp[21]~padio ;
wire \outp[20]~padio ;
wire \outp[19]~padio ;
wire \outp[18]~padio ;
wire \outp[17]~padio ;
wire \outp[16]~padio ;
wire \outp[15]~padio ;
wire \outp[14]~padio ;
wire \outp[13]~padio ;
wire \outp[12]~padio ;
wire \outp[11]~padio ;
wire \outp[10]~padio ;
wire \outp[9]~padio ;
wire \outp[8]~padio ;
wire \outp[7]~padio ;
wire \outp[6]~padio ;
wire \outp[5]~padio ;
wire \outp[4]~padio ;
wire \outp[3]~padio ;
wire \outp[2]~padio ;
wire \outp[1]~padio ;
wire \outp[0]~padio ;
wire \inp[31]~padio ;
wire \inp[30]~padio ;
wire \inp[29]~padio ;
wire \inp[28]~padio ;
wire \inp[27]~padio ;
wire \inp[26]~padio ;
wire \inp[25]~padio ;
wire \inp[24]~padio ;
wire \inp[23]~padio ;
wire \inp[22]~padio ;
wire \inp[21]~padio ;
wire \inp[20]~padio ;
wire \inp[19]~padio ;
wire \inp[18]~padio ;
wire \inp[17]~padio ;
wire \inp[16]~padio ;
wire \inp[15]~padio ;
wire \inp[14]~padio ;
wire \inp[13]~padio ;
wire \inp[12]~padio ;
wire \inp[11]~padio ;
wire \inp[10]~padio ;
wire \inp[9]~padio ;
wire \inp[8]~padio ;
wire \inp[7]~padio ;
wire \inp[6]~padio ;
wire \inp[5]~padio ;
wire \inp[4]~padio ;
wire \inp[3]~padio ;
wire \inp[2]~padio ;
wire \inp[1]~padio ;
wire \inp[0]~padio ;
wire \P1~padio ;
wire \P1~combout ;
wire \rst~combout ;
wire \inp[11]~combout ;
wire \Instance0|G_75_Z ;
wire \Instance0|G_7_0_and2 ;
wire \Instance0|G_7_0_1062_Z ;
wire \Instance0|G_83_Z ;
wire \Instance0|Instance0|ir_Out_4_ ;
wire \Instance0|G_5_0_and2_0_Z ;
wire \Instance0|G_5_0_and2_1015_Z ;
wire \Instance0|Instance0|ir_Out_2 ;
wire \Instance0|Instance0|ir_Out_3 ;
wire \Instance0|Instance0|Z_Dones_1_0 ;
wire \Instance0|Instance0|G_316_i ;
wire \Instance0|Instance0|un13_globals_pc_Out_0_i ;
wire \Instance0|Instance0|G_284 ;
wire \Instance0|Instance0|SeqChain_5[0] ;
wire \Instance0|Instance0|G_299 ;
wire \Instance0|Instance0|SeqChain_3[0] ;
wire \Instance0|Instance0|SeqChain_2[0] ;
wire \Instance0|Instance0|SeqChain[0] ;
wire \Instance0|Instance0|W_14[0] ;
wire \Instance0|Instance0|globals_StartOut_out_0 ;
wire \Instance0|Instance0|SeqChain_6[0] ;
wire \Instance0|Instance0|G_286 ;
wire \Instance0|Instance0|Loop_2[0] ;
wire \Instance0|Instance0|Loop[0] ;
wire \Instance0|Instance0|SeqChain_7[0] ;
wire \Instance0|Instance0|Loop_1_0 ;
wire \Instance0|Instance0|SeqChain_8[0] ;
wire \Instance0|Instance0|SeqChain_1[0] ;
wire \Instance0|Instance0|ThenDone[0] ;
wire \Instance0|Instance0|SeqChain_4[0] ;
wire \Instance0|Instance0|globals_CForkIn_out_0_0_or2_0_1025_cascout ;
wire \Instance0|Instance0|globals_CForkIn_out_0_0_or2_0_1027 ;
wire \Instance0|Instance0|globals_CForkIn_out_0_0_or2[0] ;
wire \Instance0|Instance0|G_65_i_i_and2_i_cascout ;
wire \Instance0|Instance0|G_65_i_i ;
wire \Instance0|Instance0|globals_pc_Out_out_0 ;
wire \Instance0|Instance0|ir_Out_6_ ;
wire \Instance0|Instance0|globals_pc_Out_out_cout[0] ;
wire \Instance0|Instance0|globals_pc_Out_out_cout[1] ;
wire \Instance0|Instance0|globals_pc_Out_out_2 ;
wire \Instance0|Instance0|globals_pc_Out_out_cout[2] ;
wire \Instance0|Instance0|globals_pc_Out_out_3 ;
wire \Instance0|Instance0|ir_Out_5_ ;
wire \Instance0|Instance0|globals_pc_Out_out_1 ;
wire \Instance0|G_4_0_and2_Z ;
wire \Instance0|Instance0|ir_Out_1 ;
wire \Instance0|Instance0|LinkWire_3_0_and2_0_and2_0_ ;
wire \I_241_i_Z~CASCOUT ;
wire \Instance0|Instance0|RAM_data_RdAddr_0_and2_0_and2_0_ ;
wire \I_241_i_rep2~CASCOUT ;
wire \Instance0|Instance0|RAM_data_RdAddr_0_and2_0_and2_1_ ;
wire \I_241_i_rep1~CASCOUT ;
wire \Instance0|Instance0|RAM_data_RdAddr_0_and2_0_and2_2_ ;
wire \I_241_i_rep0~CASCOUT ;
wire \Instance0|Instance0|RAM_data_RdAddr_0_and2_0_and2_3_ ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[11] ;
wire \Instance0|Instance0|waddr_reg1[2] ;
wire \Instance0|Instance0|I_3_2 ;
wire \Instance0|Instance0|waddr_reg1[3] ;
wire \Instance0|Instance0|I_2 ;
wire \Instance0|Instance0|waddr_reg1[1] ;
wire \Instance0|Instance0|waddr_reg1[0] ;
wire \Instance0|Instance0|I_3_NE_1_cascout ;
wire \Instance0|Instance0|I_4 ;
wire \Instance0|Instance0|dout_tmp12_11 ;
wire I_496_Z;
wire \inp[10]~combout ;
wire \inp[9]~combout ;
wire \inp[8]~combout ;
wire \inp[7]~combout ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[7] ;
wire \Instance0|Instance0|dout_tmp12_7 ;
wire I_396_Z;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[6] ;
wire \Instance0|Instance0|dout_tmp12[6] ;
wire \Instance0|Instance0|DOUT_6 ;
wire \inp[5]~combout ;
wire I_322_1;
wire I_310_1074_Z;
wire \inp[3]~combout ;
wire I_328;
wire I_311;
wire I_312_1085_Z;
wire I_332_2;
wire \inp[2]~combout ;
wire I_291_1081;
wire I_291_1082_i_Z;
wire \Instance0|Instance0|dout_tmp12[1] ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[1] ;
wire \Instance0|Instance0|DOUT[1] ;
wire \Instance0|Instance0|BinOpOut_5_add0 ;
wire \Instance0|Instance0|BinOpOut_3_add0 ;
wire I_238_Z;
wire \inp[0]~combout ;
wire I_249_1075;
wire I_249_1076_Z;
wire \Instance0|Instance0|G_294 ;
wire \Instance0|Instance0|G_296 ;
wire \Instance0|Instance0|un1_LinkWire_5_2_i_0 ;
wire \Instance0|Instance0|globals_x_Out_out_0_ ;
wire \Instance0|Instance0|dout_tmp12[0] ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[0] ;
wire \Instance0|Instance0|DOUT[0] ;
wire \Instance0|Instance0|BinOpOut_3_carry_0 ;
wire \Instance0|Instance0|BinOpOut_3_add1 ;
wire \Instance0|Instance0|BinOpOut_5_carry_0 ;
wire \Instance0|Instance0|BinOpOut_5_add1 ;
wire I_259_Z;
wire \inp[1]~combout ;
wire I_270_1078;
wire I_270_1079_Z;
wire \Instance0|Instance0|globals_x_Out_out_1_ ;
wire \Instance0|Instance0|BinOpOut_3_carry_1 ;
wire \Instance0|Instance0|BinOpOut_3_add2 ;
wire \Instance0|Instance0|BinOpOut_5_carry_1 ;
wire \Instance0|Instance0|BinOpOut_5_add2 ;
wire I_280_Z;
wire \Instance0|Instance0|globals_x_Out_out_2_ ;
wire \Instance0|Instance0|dout_tmp12[2] ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[2] ;
wire \Instance0|Instance0|DOUT[2] ;
wire \Instance0|Instance0|BinOpOut_3_carry_2 ;
wire \Instance0|Instance0|BinOpOut_3_add3 ;
wire \Instance0|Instance0|BinOpOut_5_carry_2 ;
wire \Instance0|Instance0|BinOpOut_5_add3 ;
wire I_301_Z;
wire \Instance0|Instance0|globals_x_Out_out_3_ ;
wire \Instance0|Instance0|dout_tmp12[3] ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[3] ;
wire \Instance0|Instance0|DOUT[3] ;
wire \Instance0|Instance0|BinOpOut_3_carry_3 ;
wire \Instance0|Instance0|BinOpOut_3_add4 ;
wire \Instance0|Instance0|BinOpOut_5_carry_3 ;
wire \Instance0|Instance0|BinOpOut_5_add4 ;
wire I_322_Z;
wire \inp[4]~combout ;
wire I_333_1088_Z;
wire \Instance0|Instance0|globals_x_Out_out_4_ ;
wire \Instance0|Instance0|dout_tmp12[4] ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[4] ;
wire \Instance0|Instance0|DOUT[4] ;
wire \Instance0|Instance0|BinOpOut_3_carry_4 ;
wire \Instance0|Instance0|BinOpOut_3_add5 ;
wire \Instance0|Instance0|BinOpOut_5_carry_4 ;
wire \Instance0|Instance0|BinOpOut_5_add5 ;
wire I_349_a0_i_cascout;
wire I_349_Z;
wire \Instance0|Instance0|globals_x_Out_out_5_ ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[5] ;
wire \Instance0|Instance0|dout_tmp12_5 ;
wire I_346_Z;
wire \Instance0|Instance0|BinOpOut_3_carry_5 ;
wire \Instance0|Instance0|BinOpOut_3_add6 ;
wire \Instance0|Instance0|BinOpOut_5_carry_5 ;
wire \Instance0|Instance0|BinOpOut_5_add6 ;
wire \inp[6]~combout ;
wire I_374_a0_i_cascout;
wire I_374_Z;
wire \Instance0|Instance0|globals_x_Out_out_6_ ;
wire \Instance0|Instance0|BinOpOut_3_carry_6 ;
wire \Instance0|Instance0|BinOpOut_3_add7 ;
wire \Instance0|Instance0|BinOpOut_5_carry_6 ;
wire \Instance0|Instance0|BinOpOut_5_add7 ;
wire I_399_a0_i_cascout;
wire I_399_Z;
wire \Instance0|Instance0|globals_x_Out_out_7_ ;
wire \Instance0|Instance0|BinOpOut_3_carry_7 ;
wire \Instance0|Instance0|BinOpOut_3_add8 ;
wire \Instance0|Instance0|BinOpOut_5_carry_7 ;
wire \Instance0|Instance0|BinOpOut_5_add8 ;
wire I_424_a0_i_cascout;
wire I_424_Z;
wire \Instance0|Instance0|globals_x_Out_out_8_ ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[8] ;
wire \Instance0|Instance0|dout_tmp12_8 ;
wire I_421_Z;
wire \Instance0|Instance0|BinOpOut_3_carry_8 ;
wire \Instance0|Instance0|BinOpOut_3_add9 ;
wire \Instance0|Instance0|BinOpOut_5_carry_8 ;
wire \Instance0|Instance0|BinOpOut_5_add9 ;
wire I_449_a0_i_cascout;
wire I_449_Z;
wire \Instance0|Instance0|globals_x_Out_out_9_ ;
wire \Instance0|Instance0|dout_tmp12_9 ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[9] ;
wire I_446_Z;
wire \Instance0|Instance0|BinOpOut_3_carry_9 ;
wire \Instance0|Instance0|BinOpOut_3_add10 ;
wire \Instance0|Instance0|BinOpOut_5_carry_9 ;
wire \Instance0|Instance0|BinOpOut_5_add10 ;
wire I_474_a0_i_cascout;
wire I_474_Z;
wire \Instance0|Instance0|globals_x_Out_out_10_ ;
wire \Instance0|Instance0|RAM_data_I_1|U1|q[10] ;
wire \Instance0|Instance0|dout_tmp12_10 ;
wire I_471_Z;
wire \Instance0|Instance0|BinOpOut_3_carry_10 ;
wire \Instance0|Instance0|BinOpOut_3_add11 ;
wire \Instance0|Instance0|BinOpOut_5_carry_10 ;
wire \Instance0|Instance0|BinOpOut_5_add11 ;
wire I_499_a0_i_cascout;