rm16x16.bde

FIFo参考设计16x32 FIFO with simultaneous read/write operations.

SCHM0102

HEADER
{
 FREEID 3030
 VARIABLES
 {
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #CELL="RM16X16"
  #LANGUAGE="EDIF"
  AUTHOR="ALDEC"
  COMPANY="ALDEC"
  CREATIONDATE="14/12/99"
  TITLE="RM16X16"
 }
 SYMBOL "spartan2" "RAM16X1D" "RAM16X1D"
 {
  HEADER
  {
   VARIABLES
   {
    #BLACK_BOX="1"
    #DESCRIPTION="Positive Edge-Triggered Dual Port Select RAM"
    #GENERIC0="TimingChecksOn:BOOLEAN:=False"
    #GENERIC1="InstancePath:STRING:=\"*\""
    #GENERIC10="tipd_DPRA2:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC11="tipd_DPRA3:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC12="tipd_D:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC13="tipd_WE:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC14="tipd_WCLK:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC15="tpd_A0_SPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC16="tpd_A1_SPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC17="tpd_A2_SPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC18="tpd_A3_SPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC19="tpd_WCLK_SPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC2="Xon:BOOLEAN:=True"
    #GENERIC20="tpd_DPRA0_DPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC21="tpd_DPRA1_DPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC22="tpd_DPRA2_DPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC23="tpd_DPRA3_DPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC24="tpd_WCLK_DPO:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC25="tsetup_D_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC26="tsetup_D_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC27="tsetup_WE_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC28="tsetup_WE_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC29="tsetup_A0_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC3="MsgOn:BOOLEAN:=False"
    #GENERIC30="tsetup_A0_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC31="tsetup_A1_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC32="tsetup_A1_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC33="tsetup_A2_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC34="tsetup_A2_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC35="tsetup_A3_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC36="tsetup_A3_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC37="thold_D_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC38="thold_D_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC39="thold_WE_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC4="tipd_A0:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC40="thold_WE_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC41="thold_A0_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC42="thold_A0_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC43="thold_A1_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC44="thold_A1_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC45="thold_A2_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC46="thold_A2_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC47="thold_A3_WCLK_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC48="thold_A3_WCLK_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC49="tpw_WCLK_posedge:VitalDelayType:=0.0 ns"
    #GENERIC5="tipd_A1:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC50="tpw_WCLK_negedge:VitalDelayType:=0.0 ns"
    #GENERIC51="INIT:BIT_VECTOR(15 downto 0):=X\"0000\""
    #GENERIC6="tipd_A2:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC7="tipd_A3:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC8="tipd_DPRA0:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC9="tipd_DPRA1:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #LANGUAGE="VHDL"
    #MODIFIED="1039089001"
    #NO_SYMBOL_NAME="1"
    #NO_SYMBOL_REFERENCE="1"
    LEVEL="XILINX"
    LIBVER="2.0.0"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,260,560)
    FREEID 30
   }
   
   BODY
   {
    TEXT  2, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,189,74,211)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 1
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  4, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,229,74,251)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 3
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  6, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,269,74,291)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 5
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  8, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,309,74,331)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 7
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  10, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,109,64,131)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 9
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  12, 0, 0
    {
     TEXT "$#NAME"
     RECT (168,189,210,211)
     ALIGN 6
     COLOR (0,0,255)
     PARENT 11
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  14, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,349,115,371)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 13
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  16, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,389,115,411)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 15
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  18, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,429,115,451)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 17
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  20, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,469,115,491)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 19
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  22, 0, 0
    {
     TEXT "$#NAME"
     RECT (169,109,210,131)
     ALIGN 6
     COLOR (0,0,255)
     PARENT 21
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  24, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,149,107,171)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 23
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    TEXT  26, 0, 0
    {
     TEXT "$#NAME"
     RECT (50,69,82,91)
     ALIGN 4
     COLOR (0,0,255)
     PARENT 25
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    LINE  27, 0, 0
    {
     OUTLINE 0,1, (0,0,191)
     POINTS ( (40,150), (50,160), (40,170) )
     FILL (1,(0,254,255),0)
    }
    RECT  28, 0, 0
    {
     OUTLINE 0,1, (0,0,191)
     AREA (40,40,220,520)
     FILL (1,(0,254,255),0)
    }
    TEXT  29, 0, 0
    {
     TEXT "RAM16X1D"
     RECT (89,18,191,40)
     ALIGN 9
     COLOR (191,0,191)
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    PIN  1, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="A0"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="2"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  3, 0, 0
    {
     COORD (0,240)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="A1"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="3"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  5, 0, 0
    {
     COORD (0,280)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="A2"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="4"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  7, 0, 0
    {
     COORD (0,320)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="A3"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="5"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  9, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="D"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="1"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  11, 0, 0
    {
     COORD (260,200)
     VARIABLES
     {
      #DIRECTION="OUT"
      #NAME="DPO"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="OUT"
      port_id="18"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (-40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  13, 0, 0
    {
     COORD (0,360)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="DPRA0"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="10"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  15, 0, 0
    {
     COORD (0,400)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="DPRA1"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="11"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  17, 0, 0
    {
     COORD (0,440)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="DPRA2"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="12"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  19, 0, 0
    {
     COORD (0,480)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="DPRA3"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="13"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  21, 0, 0
    {
     COORD (260,120)
     VARIABLES
     {
      #DIRECTION="OUT"
      #NAME="SPO"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="OUT"
      port_id="7"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (-40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  23, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="WCLK"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="8"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  25, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="WE"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="6"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
   }
  }
 }
}

PAGE ""
{
 PAGEHEADER
 {
  PAGESIZE (4400,3400)
  MARGINS (0,0,0,0)
  RECT (0,0,0,0)
 }
 
 BODY
 {
  VTX  3, 0, 0
  {
   COORD (400,500)
  }
  VTX  4, 0, 0
  {
   COORD (900,500)
  }
  VTX  5, 0, 0
  {
   COORD (400,580)
  }
  VTX  6, 0, 0
  {
   COORD (900,580)
  }
  VTX  7, 0, 0
  {
   COORD (3120,3100)
  }
  VTX  8, 0, 0
  {
   COORD (3400,1840)
  }
  VTX  9, 0, 0
  {
   COORD (3400,1200)
  }
  VTX  10, 0, 0
  {
   COORD (3080,3100)
  }
  VTX  11, 0, 0
  {
   COORD (3040,3100)
  }
  VTX  12, 0, 0
  {
   COORD (3400,540)
  }
  VTX  13, 0, 0
  {
   COORD (900,740)
  }
  VTX  14, 0, 0
  {
   COORD (660,740)
  }
  VTX  17, 0, 0
  {
   COORD (900,660)
  }
  VTX  18, 0, 0
  {
   COORD (660,660)
  }
  VTX  19, 0, 0
  {
   COORD (900,700)
  }
  VTX  20, 0, 0
  {
   COORD (660,700)
  }
  VTX  21, 0, 0
  {
   COORD (900,1160)
  }
  VTX  22, 0, 0
  {
   COORD (780,1160)
  }
  VTX  23, 0, 0
  {
   COORD (900,1240)
  }
  VTX  24, 0, 0
  {
   COORD (780,1240)
  }
  VTX  25, 0, 0
  {
   COORD (900,1280)
  }
  VTX  26, 0, 0
  {
   COORD (780,1280)
  }
  VTX  27, 0, 0
  {
   COORD (900,1320)
  }
  VTX  28, 0, 0
  {
   COORD (780,1320)
  }
  VTX  29, 0, 0
  {
   COORD (900,1360)
  }
  VTX  30, 0, 0
  {
   COORD (780,1360)
  }
  VTX  31, 0, 0
  {
   COORD (900,1400)
  }
  VTX  32, 0, 0
  {
   COORD (780,1400)
  }
  VTX  33, 0, 0
  {
   COORD (900,1440)
  }
  VTX  34, 0, 0
  {
   COORD (780,1440)
  }
  VTX  35, 0, 0
  {
   COORD (900,1480)
  }
  VTX  36, 0, 0
  {
   COORD (780,1480)
  }
  VTX  37, 0, 0
  {
   COORD (900,1520)
  }
  VTX  38, 0, 0
  {
   COORD (780,1520)
  }
  VTX  39, 0, 0
  {
   COORD (900,1560)
  }
  VTX  40, 0, 0
  {
   COORD (780,1560)
  }
  VTX  41, 0, 0
  {
   COORD (900,1800)
  }
  VTX  42, 0, 0
  {
   COORD (780,1800)
  }
  VTX  43, 0, 0
  {
   COORD (900,1880)
  }
  VTX  44, 0, 0
  {
   COORD (780,1880)
  }
  VTX  45, 0, 0
  {
   COORD (900,1920)
  }
  VTX  46, 0, 0
  {
   COORD (780,1920)
  }
  VTX  47, 0, 0
  {
   COORD (900,1960)
  }
  VTX  48, 0, 0
  {
   COORD (780,1960)
  }
  VTX  49, 0, 0
  {
   COORD (900,2000)
  }
  VTX  50, 0, 0
  {
   COORD (780,2000)
  }
  VTX  51, 0, 0
  {
   COORD (900,2040)
  }
  VTX  52, 0, 0
  {
   COORD (780,2040)
  }
  VTX  53, 0, 0
  {
   COORD (900,2080)
  }
  VTX  54, 0, 0
  {
   COORD (780,2080)
  }
  VTX  55, 0, 0
  {
   COORD (900,2120)
  }
  VTX  56, 0, 0
  {
   COORD (780,2120)
  }
  VTX  57, 0, 0
  {
   COORD (900,2160)
  }
  VTX  58, 0, 0
  {
   COORD (780,2160)
  }
  VTX  59, 0, 0
  {
   COORD (900,2200)
  }
  VTX  60, 0, 0
  {
   COORD (780,2200)
  }
  VTX  61, 0, 0
  {
   COORD (900,2460)
  }
  VTX  62, 0, 0
  {
   COORD (780,2460)
  }
  VTX  63, 0, 0
  {
   COORD (900,2540)
  }
  VTX  64, 0, 0
  {
   COORD (780,2540)
  }
  VTX  65, 0, 0
  {
   COORD (900,2580)
  }
  VTX  66, 0, 0
  {
   COORD (780,2580)
  }
  VTX  67, 0, 0
  {
   COORD (900,2620)
  }
  VTX  68, 0, 0
  {
   COORD (780,2620)
  }
  VTX  69, 0, 0
  {
   COORD (900,2660)
  }
  VTX  70, 0, 0
  {
   COORD (780,2660)
  }
  VTX  71, 0, 0
  {
   COORD (900,2700)
  }
  VTX  72, 0, 0
  {
   COORD (780,2700)
  }
  VTX  73, 0, 0
  {
   COORD (900,2740)
  }
  VTX  74, 0, 0