fd16d.bde

FIFo参考设计16x32 FIFO with simultaneous read/write operations.

SCHM0102

HEADER
{
 FREEID 1887
 VARIABLES
 {
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #CELL="FD16D"
  #LANGUAGE="EDIF"
  AUTHOR="ALDEC"
  COMPANY="ALDEC"
  CREATIONDATE="14/12/99"
  TITLE="FD16D"
 }
 SYMBOL "spartan2" "FDCE" "FDCE"
 {
  HEADER
  {
   VARIABLES
   {
    #BLACK_BOX="1"
    #DESCRIPTION="D Flip-Flop with Clock Enable and Asynchronous Clear"
    #GENERIC0="TimingChecksOn:BOOLEAN:=False"
    #GENERIC1="InstancePath:STRING:=\"*\""
    #GENERIC10="thold_D_C_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC11="tsetup_CE_C_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC12="tsetup_CE_C_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC13="thold_CE_C_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC14="thold_CE_C_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC15="trecovery_CLR_C_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC16="thold_CLR_C_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC17="tpw_C_posedge:VitalDelayType:=0.0 ns"
    #GENERIC18="tpw_CLR_posedge:VitalDelayType:=0.0 ns"
    #GENERIC19="tpw_C_negedge:VitalDelayType:=0.0 ns"
    #GENERIC2="Xon:BOOLEAN:=True"
    #GENERIC20="tipd_D:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC21="tipd_C:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC22="tipd_CE:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC23="tipd_CLR:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC3="MsgOn:BOOLEAN:=False"
    #GENERIC4="INIT:STRING:=\"R\""
    #GENERIC5="tpd_CLR_Q:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC6="tpd_C_Q:VitalDelayType01:=(0.0 ns,0.0 ns)"
    #GENERIC7="tsetup_D_C_posedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC8="tsetup_D_C_negedge_posedge:VitalDelayType:=0.0 ns"
    #GENERIC9="thold_D_C_posedge_posedge:VitalDelayType:=0.0 ns"
    #LANGUAGE="VHDL"
    #MODIFIED="1016718410"
    #NO_SYMBOL_NAME="1"
    #NO_SYMBOL_REFERENCE="1"
    DEVICE="DFF"
    INIT="R"
    LEVEL="XILINX"
    LIBVER="2.0.0"
   }
  }
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    {
     TEXT "$#NAME"
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    TEXT  4, 0, 0
    {
     TEXT "$#NAME"
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     ALIGN 4
     COLOR (0,0,255)
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    TEXT  6, 0, 0
    {
     TEXT "$#NAME"
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    RECT  11, 0, 0
    {
     OUTLINE 0,1, (0,0,191)
     AREA (40,40,200,200)
     FILL (1,(0,255,255),0)
    }
    LINE  12, 0, 0
    {
     OUTLINE 0,1, (0,0,191)
     POINTS ( (40,220), (120,220), (120,200) )
     FILL (1,(0,255,255),0)
    }
    LINE  13, 0, 0
    {
     OUTLINE 0,1, (0,0,191)
     POINTS ( (40,150), (50,160), (40,170) )
     FILL (1,(0,255,255),0)
    }
    TEXT  14, 0, 0
    {
     TEXT "FDCE"
     RECT (94,18,147,40)
     ALIGN 9
     COLOR (191,0,191)
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    PIN  1, 0, 0
    {
     COORD (0,160)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="C"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="3"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  3, 0, 0
    {
     COORD (0,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="CE"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="2"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  5, 0, 0
    {
     COORD (0,220)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="CLR"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="6"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  7, 0, 0
    {
     COORD (0,80)
     VARIABLES
     {
      #DIRECTION="IN"
      #NAME="D"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="IN"
      port_id="1"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
    PIN  9, 0, 0
    {
     COORD (240,80)
     VARIABLES
     {
      #DIRECTION="OUT"
      #NAME="Q"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="OUT"
      port_id="4"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (-40,0), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
   }
  }
 }
 SYMBOL "spartan2" "GND" "GND"
 {
  HEADER
  {
   VARIABLES
   {
    #BLACK_BOX="1"
    #DESCRIPTION="Ground-Connection Signal Tag"
    #GENERIC0="TimingChecksOn:BOOLEAN:=False"
    #GENERIC1="InstancePath:STRING:=\"*\""
    #GENERIC2="Xon:BOOLEAN:=True"
    #GENERIC3="MsgOn:BOOLEAN:=False"
    #LANGUAGE="VHDL"
    #MODIFIED="1048697857"
    #NO_SYMBOL_NAME="1"
    #NO_SYMBOL_REFERENCE="1"
    LEVEL="XILINX"
    LIBVER="2.0.0"
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     OUTLINE 0,1, (0,0,191)
     POINTS ( (40,20), (40,40) )
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    LINE  4, 0, 0
    {
     OUTLINE 0,1, (0,0,191)
     POINTS ( (32,50), (48,50) )
     FILL (1,(0,255,255),0)
    }
    LINE  5, 0, 0
    {
     OUTLINE 0,1, (0,0,191)
     POINTS ( (38,60), (42,60) )
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    LINE  6, 0, 0
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     OUTLINE 0,1, (0,0,191)
     POINTS ( (26,40), (54,40) )
     FILL (1,(0,255,255),0)
    }
    LINE  7, 0, 0
    {
     OUTLINE 0,1, (0,0,191)
     POINTS ( (40,30), (40,40) )
     FILL (1,(0,255,255),0)
    }
    TEXT  8, 0, 0
    {
     TEXT "GND"
     RECT (10,58,52,80)
     ALIGN 8
     COLOR (191,0,191)
     FONT (8,0,0,400,0,0,0,"Arial")
    }
    PIN  1, 0, 0
    {
     COORD (40,0)
     VARIABLES
     {
      #DIRECTION="OUT"
      #INITIAL_VALUE="'0'"
      #NAME="G"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
      PINTYPE="OUT"
      port_id="4"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,191)
      POINTS ( (0,20), (0,0) )
      FILL (1,(0,0,0),0)
     }
    }
   }
  }
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 SYMBOL "spartan2" "VCC" "VCC"
 {
  HEADER
  {
   VARIABLES
   {
    #BLACK_BOX="1"
    #DESCRIPTION="VCC-Connection Signal Tag"
    #GENERIC0="TimingChecksOn:BOOLEAN:=False"
    #GENERIC1="InstancePath:STRING:=\"*\""
    #GENERIC2="Xon:BOOLEAN:=True"
    #GENERIC3="MsgOn:BOOLEAN:=False"
    #LANGUAGE="VHDL"
    #MODIFIED="1048697843"
    #NO_SYMBOL_NAME="1"
    #NO_SYMBOL_REFERENCE="1"
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    LINE  4, 0, 0
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    PIN  1, 0, 0
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     COORD (40,80)
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     {
      #DIRECTION="OUT"
      #INITIAL_VALUE="'1'"
      #NAME="P"
      #NUMBER="0"
      #VHDL_TYPE="std_ulogic"
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      port_id="2"
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     LINE  1, 0, 0
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      OUTLINE 0,1, (0,0,191)
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