fifo_bde.adf

FIFo参考设计16x32 FIFO with simultaneous read/write operations.

[Project]
Current Flow=Multivendor
VCS=0
version=1
modified=32
Current Config=compile

[Configurations]
compile=fifo_bde

[Library]
fifo_bde=.\fifo_bde.LIB

[Groups]

[Settings]
FLOW_TYPE=Schematic
LANGUAGE=VHDL
FAMILY=
SYNTH_TOOL=<none>
IMPL_TOOL=<none>
FLOWTOOLS=ONLY_IMPL
SYNTH_STATUS=NONE
C_SERVER_SIM=NONE
ON_SERVERFARM_SIM=0
C_SERVER_SYNTH=NONE
ON_SERVERFARM_SYNTH=0
C_SERVER_IMPL=NONE
ON_SERVERFARM_IMPL=0
UseCeloxica=0
CSYNTH_TOOL=<none>
Celoxica=0
REFRESH_FLOW=1

[$LibMap$]
Active_lib=SPARTAN2
xilinxun=SPARTAN2
SYNTH_TOOL=SYNOPSYS
FLOWTOOLS=IMPL_WITH_SYNTH
IMPL_TOOL=XILINX
fifo_bde=.
UnlinkedDesignLibrary=SPARTAN2
DESIGNS=SPARTAN2

[SYNTHESIS]
FAMILY=
CeloxicaPath=

[IMPLEMENTATION]
FAMILY=

[HierarchyViewer]
SortInfo=u
HierarchyInformation=
ShowHide=ShowTopLevel
Selected=

[ORDER]
autorefresh=0
macro_path=
macro_name=
modified=1
Synchronize=1

[Files]
/readme.txt=-1
/fd16d.bde=-1
/c4u.bde=-1
/c4ud.bde=-1
/fifod.bde=-1
/rm16x32.bde=-1
/rm16x16.bde=-1
/fifo.bde=-1
TB_verilog/fifo_TB.v=-1
TB_verilog/fifo_TB_runtest.do=-1
TB_vhd/fifo_TB.vhd=-1
TB_vhd/fifo_TB_runtest.do=-1

[Files.Data]
.\src\readme.txt=Text File
.\src\fd16d.bde=Block Diagram
.\src\c4u.bde=Block Diagram
.\src\c4ud.bde=Block Diagram
.\src\fifod.bde=Block Diagram
.\src\rm16x32.bde=Block Diagram
.\src\rm16x16.bde=Block Diagram
.\src\fifo.bde=Block Diagram
.\src\TB_verilog\fifo_TB.v=Verilog Source Code
.\src\TB_verilog\fifo_TB_runtest.do=Macro
.\src\TB_vhd\fifo_TB.vhd=VHDL Source Code
.\src\TB_vhd\fifo_TB_runtest.do=Macro