jpeg_tb.v
来自「Pure hardware JPEG Encoder design. Packa」· Verilog 代码 · 共 129 行
V
129 行
module jpeg_tb;parameter CAPTURE_ORAM = "OUT_RAM.txt", CAPTURE_BIN = "test_out.jpg";integer f_capture, f_capture_bin;wire CLK;wire RST;wire [23:0] ram_rdaddr;wire [7:0] ram_q,ram_byte; wire ram_wren; wire [23:0] ram_wraddr; wire [31:0] OPB_ABus; wire [3:0] OPB_BE; wire [31:0] OPB_DBus_in; wire OPB_RNW; wire OPB_select; wire [31:0] OPB_DBus_out; wire OPB_XferAck; wire OPB_retry; wire OPB_toutSup; wire OPB_errAck; wire [19:0] iram_waddr; wire [19:0] iram_raddr; wire [23:0] iram_wdata; wire [23:0] iram_rdata; wire iram_wren; wire iram_rden; wire sim_done; wire iram_fifo_afull;ClkGen U_ClkGen( .CLK (CLK), .RST (RST));// ------------------------------// -- HOST Bus Functional Model// ------------------------------HostBFM U_HostBFM( .CLK ( CLK), .RST ( RST), //-- OPB .OPB_ABus ( OPB_ABus), .OPB_BE ( OPB_BE), .OPB_DBus_in ( OPB_DBus_in), .OPB_RNW ( OPB_RNW), .OPB_select ( OPB_select), .OPB_DBus_out ( OPB_DBus_out), .OPB_XferAck ( OPB_XferAck), .OPB_retry ( OPB_retry), .OPB_toutSup ( OPB_toutSup), .OPB_errAck ( OPB_errAck), //-- IRAM .iram_wdata ( iram_wdata), .iram_wren ( iram_wren), .fifo_almost_full ( iram_fifo_afull), .sim_done ( sim_done) ); // ------------------------------// -- JPEG ENCODER// ------------------------------JpegEnc U_JpegEnc ( .CLK ( CLK), .RST ( RST), //-- OPB .OPB_ABus ( OPB_ABus), .OPB_BE ( OPB_BE), .OPB_DBus_in ( OPB_DBus_in), .OPB_RNW ( OPB_RNW), .OPB_select ( OPB_select), .OPB_DBus_out ( OPB_DBus_out), .OPB_XferAck ( OPB_XferAck), .OPB_retry ( OPB_retry), .OPB_toutSup ( OPB_toutSup), .OPB_errAck ( OPB_errAck), //-- IMAGE RAM .iram_wdata ( iram_wdata), .iram_wren ( iram_wren), .iram_fifo_afull ( iram_fifo_afull), //-- OUT RAM .ram_byte ( ram_byte), .ram_wren ( ram_wren), .ram_wraddr ( ram_wraddr) );// -------------------------------------------------------------------// -- OUT RAM// -------------------------------------------------------------------RAMSIM #(18,8) U_OUT_RAM ( .d ( ram_byte), .waddr ( ram_wraddr[17:0]), .raddr ( ram_rdaddr[17:0]), .we ( ram_wren), .clk ( CLK), .q ( ram_q) ); initialbegin f_capture = $fopen(CAPTURE_ORAM); f_capture_bin = $fopen(CAPTURE_BIN); while(sim_done!=1) begin @(posedge CLK); if(ram_wren) begin $fwriteb(f_capture_bin,"%c",ram_byte); end end $fclose(f_capture); $fclose(f_capture_bin); //$finish;endendmodule
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