_primary.vhd

来自「Pure hardware JPEG Encoder design. Packa」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity HeaderRam is
    port(
        d               : in     vl_logic_vector(7 downto 0);
        waddr           : in     vl_logic_vector(9 downto 0);
        raddr           : in     vl_logic_vector(9 downto 0);
        we              : in     vl_logic;
        clk             : in     vl_logic;
        q               : out    vl_logic_vector(7 downto 0)
    );
end HeaderRam;