__model_tech_.._verilog__info

来自「Pure hardware JPEG Encoder design. Packa」· _VERILOG__INFO 代码 · 共 55 行

m255
cModel Technology Builtin Library
13
dD:\qa\patch6_2\nightly\master\modeltech
Pvl_resolve
OL;C;6.2c;35
31
b1
OP;C;6.2c;35
d.
F$MODEL_TECH/../vhdl_src/verilog/vlresolve.vhd
l0
L9
V?GckcDU8_EkiBzeFQFJ203
OE;C;6.2c;35
o-93 -work verilog -path $MODEL_TECH/../vhdl_src/verilog/vlresolve.vhd
tExplicit 1
Bbody
DB work vl_resolve ?GckcDU8_EkiBzeFQFJ203
OL;C;6.2c;35
31
OP;C;6.2c;35
l0
L9
VB2T>5lW9_]oCAaQD64C2n3
OE;C;6.2c;35
o-93 -work verilog -path $MODEL_TECH/../vhdl_src/verilog/vlresolve.vhd
tExplicit 1
nbody
Pvl_types
OL;C;6.2c;35
31
b1
OP;C;6.2c;35
d.
F$MODEL_TECH/../vhdl_src/verilog/vltypes.vhd
l0
L9
VEL`7Km5528[`SUe@0N=SW0
OE;C;6.2c;35
o-93 -work verilog -path $MODEL_TECH/../vhdl_src/verilog/vltypes.vhd
tExplicit 1
Bbody
DB work vl_types EL`7Km5528[`SUe@0N=SW0
OL;C;6.2c;35
31
OP;C;6.2c;35
l0
L9
VRVba`dZz<efKd;P8Y<8B10
OE;C;6.2c;35
o-93 -work verilog -path $MODEL_TECH/../vhdl_src/verilog/vltypes.vhd
tExplicit 1
nbody