📄 jpegenc.vhd
字号:
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- IMAGE RAM
iram_wdata : in std_logic_vector(23 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0)
);
end entity JpegEnc;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
signal outram_base_addr : std_logic_vector(9 downto 0);
signal num_enc_bytes : std_logic_vector(23 downto 0);
signal img_size_x : std_logic_vector(15 downto 0);
signal img_size_y : std_logic_vector(15 downto 0);
signal sof : std_logic;
signal jpg_iram_rden : std_logic;
signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);
signal jpg_iram_rdata : std_logic_vector(23 downto 0);
signal fdct_start : std_logic;
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
signal huf_ready : std_logic;
signal bs_start : std_logic;
signal bs_ready : std_logic;
signal zz_buf_sel : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal zz_data : std_logic_vector(11 downto 0);
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
signal huf_runlength : std_logic_vector(3 downto 0);
signal huf_size : std_logic_vector(3 downto 0);
signal huf_amplitude : std_logic_vector(11 downto 0);
signal huf_dval : std_logic;
signal bs_buf_sel : std_logic;
signal bs_fifo_empty : std_logic;
signal bs_rd_req : std_logic;
signal bs_packed_byte : std_logic_vector(7 downto 0);
signal huf_fifo_empty : std_logic;
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
signal cmp_max : std_logic_vector(1 downto 0);
signal image_size_reg : std_logic_vector(31 downto 0);
signal jfif_ram_byte : std_logic_vector(7 downto 0);
signal jfif_ram_wren : std_logic;
signal jfif_ram_wraddr : std_logic_vector(23 downto 0);
signal out_mux_ctrl : std_logic;
signal img_size_wr : std_logic;
signal jfif_start : std_logic;
signal jfif_ready : std_logic;
signal bs_ram_byte : std_logic_vector(7 downto 0);
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
signal fdct_block_cnt : std_logic_vector(12 downto 0);
signal fdct_fifo_rd : std_logic;
signal fdct_fifo_empty : std_logic;
signal fdct_fifo_q : std_logic_vector(23 downto 0);
signal fdct_fifo_hf_full : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Host Interface
-------------------------------------------------------------------
U_HostIF : entity work.HostIF
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- Quantizer RAM
qdata => qdata,
qaddr => qaddr,
qwren => qwren,
-- CTRL
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- ByteStuffer
outram_base_addr => outram_base_addr,
num_enc_bytes => num_enc_bytes,
-- global
img_size_x => img_size_x,
img_size_y => img_size_y,
img_size_wr => img_size_wr,
sof => sof,
cmp_max => cmp_max
);
-------------------------------------------------------------------
-- BUF_FIFO
-------------------------------------------------------------------
U_BUF_FIFO : entity work.BUF_FIFO
port map
(
CLK => CLK,
RST => RST,
-- HOST PROG
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof,
-- HOST DATA
iram_wren => iram_wren,
iram_wdata => iram_wdata,
fifo_almost_full => iram_fifo_afull,
-- FDCT
fdct_block_cnt => fdct_block_cnt,
fdct_fifo_rd => fdct_fifo_rd,
fdct_fifo_empty => fdct_fifo_empty,
fdct_fifo_q => fdct_fifo_q,
fdct_fifo_hf_full => fdct_fifo_hf_full
);
-------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------
U_CtrlSM : entity work.CtrlSM
port map
(
CLK => CLK,
RST => RST,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
cmp_max => cmp_max,
-- FDCT
fdct_start => fdct_start,
fdct_ready => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- ZIGZAG
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_start => rle_start,
rle_ready => rle_ready,
rle_sm_settings => rle_sm_settings,
-- Huffman
huf_start => huf_start,
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -