traffic.fnsim.qmsg

verilog HDl 交通灯的实现,而且这是有别于一般的vhdl语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 18 12:24:45 2009 " "Info: Processing started: Wed Mar 18 12:24:45 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file traffic.v" { { "Info" "ISGN_ENTITY_NAME" "1 traffic " "Info: Found entity 1: traffic" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "traffic " "Info: Elaborating entity \"traffic\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ared traffic.v(12) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(12): inferring latch(es) for variable \"ared\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ayellow traffic.v(12) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(12): inferring latch(es) for variable \"ayellow\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "agreen traffic.v(12) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(12): inferring latch(es) for variable \"agreen\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "aleft traffic.v(12) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(12): inferring latch(es) for variable \"aleft\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "bred traffic.v(12) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(12): inferring latch(es) for variable \"bred\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "byellow traffic.v(12) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(12): inferring latch(es) for variable \"byellow\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "bgreen traffic.v(12) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(12): inferring latch(es) for variable \"bgreen\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "bleft traffic.v(12) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(12): inferring latch(es) for variable \"bleft\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(60) " "Warning (10230): Verilog HDL assignment warning at traffic.v(60): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(63) " "Warning (10230): Verilog HDL assignment warning at traffic.v(63): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 63 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(115) " "Warning (10230): Verilog HDL assignment warning at traffic.v(115): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(118) " "Warning (10230): Verilog HDL assignment warning at traffic.v(118): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bleft\[0\] traffic.v(12) " "Info (10041): Inferred latch for \"bleft\[0\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bleft\[1\] traffic.v(12) " "Info (10041): Inferred latch for \"bleft\[1\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bleft\[2\] traffic.v(12) " "Info (10041): Inferred latch for \"bleft\[2\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bleft\[3\] traffic.v(12) " "Info (10041): Inferred latch for \"bleft\[3\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bleft\[4\] traffic.v(12) " "Info (10041): Inferred latch for \"bleft\[4\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bleft\[5\] traffic.v(12) " "Info (10041): Inferred latch for \"bleft\[5\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bleft\[6\] traffic.v(12) " "Info (10041): Inferred latch for \"bleft\[6\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bleft\[7\] traffic.v(12) " "Info (10041): Inferred latch for \"bleft\[7\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[0\] traffic.v(12) " "Info (10041): Inferred latch for \"bgreen\[0\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[1\] traffic.v(12) " "Info (10041): Inferred latch for \"bgreen\[1\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[2\] traffic.v(12) " "Info (10041): Inferred latch for \"bgreen\[2\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[3\] traffic.v(12) " "Info (10041): Inferred latch for \"bgreen\[3\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[4\] traffic.v(12) " "Info (10041): Inferred latch for \"bgreen\[4\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "bgreen\[5\] traffic.v(12) " "Info (10041): Inferred latch for \"bgreen\[5\]\" at traffic.v(12)" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}