cnt10.vhd

来自「本程序完整的实现了数字频率计的常用功能。并对通常数字频率计的常见问题进行了改进。」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
  port(clk:in std_logic;
       clr:in std_logic;
       en:in std_logic;
       count: out integer range 0 to 9;
       cin:out std_logic);
end entity;
architecture art of cnt10 is
  signal tem:integer range 0 to 10;
  begin
    count<=tem;
    process(clk,clr,en)
      begin
      if (clr='1') then tem<=0;
      elsif(rising_edge(clk)) then
        if(en='1') then
           if(tem=9) then
             tem<=0;
             cin<='1';
           else
             tem<=tem+1;
             cin<='0';
           end if;
        end if;
      end if;
    end process;
end art;