cnt10_8.rpt

来自「本程序完整的实现了数字频率计的常用功能。并对通常数字频率计的常见问题进行了改进。」· RPT 代码 · 共 1,118 行 · 第 1/4 页

  _EQ035 = !en &  _LC1_B16
         #  en & !_LC1_B16;

-- Node name is '|CNT10:5|:12' = '|CNT10:5|tem1' 
-- Equation name is '_LC2_B16', type is buried 
_LC2_B16 = DFFE( _EQ036,  _LC1_A16, GLOBAL(!clr),  VCC,  VCC);
  _EQ036 = !_LC1_B16 &  _LC2_B16 & !_LC5_B16
         #  en &  _LC1_B16 & !_LC2_B16 & !_LC5_B16
         # !en &  _LC2_B16;

-- Node name is '|CNT10:5|:11' = '|CNT10:5|tem2' 
-- Equation name is '_LC6_B16', type is buried 
_LC6_B16 = DFFE( _EQ037,  _LC1_A16, GLOBAL(!clr),  VCC,  VCC);
  _EQ037 =  en & !_LC5_B16 &  _LC7_B16
         # !en &  _LC6_B16;

-- Node name is '|CNT10:5|:10' = '|CNT10:5|tem3' 
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = DFFE( _EQ038,  _LC1_A16, GLOBAL(!clr),  VCC,  VCC);
  _EQ038 =  _LC4_B16 & !_LC5_B16 & !_LC8_B16
         #  en & !_LC4_B16 & !_LC5_B16 &  _LC8_B16
         # !en &  _LC4_B16;

-- Node name is '|CNT10:5|:8' 
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = DFFE( _EQ039,  _LC1_A16,  VCC,  VCC, !_LC4_A16);
  _EQ039 =  en &  _LC5_B16
         # !en &  _LC3_B16;

-- Node name is '|CNT10:5|:51' 
-- Equation name is '_LC5_B16', type is buried 
_LC5_B16 = LCELL( _EQ040);
  _EQ040 =  _LC1_B16 & !_LC2_B16 &  _LC4_B16 & !_LC6_B16;

-- Node name is '|CNT10:6|LPM_ADD_SUB:83|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B21', type is buried 
_LC6_B21 = LCELL( _EQ041);
  _EQ041 =  _LC3_B21 &  _LC5_B21 &  _LC7_B21;

-- Node name is '|CNT10:6|LPM_ADD_SUB:83|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_B21', type is buried 
_LC4_B21 = LCELL( _EQ042);
  _EQ042 = !_LC3_B21 &  _LC5_B21
         #  _LC5_B21 & !_LC7_B21
         #  _LC3_B21 & !_LC5_B21 &  _LC7_B21;

-- Node name is '|CNT10:6|:13' = '|CNT10:6|tem0' 
-- Equation name is '_LC7_B21', type is buried 
_LC7_B21 = DFFE( _EQ043,  _LC3_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ043 = !en &  _LC7_B21
         #  en & !_LC7_B21;

-- Node name is '|CNT10:6|:12' = '|CNT10:6|tem1' 
-- Equation name is '_LC3_B21', type is buried 
_LC3_B21 = DFFE( _EQ044,  _LC3_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ044 = !_LC2_B21 &  _LC3_B21 & !_LC7_B21
         #  en & !_LC2_B21 & !_LC3_B21 &  _LC7_B21
         # !en &  _LC3_B21;

-- Node name is '|CNT10:6|:11' = '|CNT10:6|tem2' 
-- Equation name is '_LC5_B21', type is buried 
_LC5_B21 = DFFE( _EQ045,  _LC3_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ045 =  en & !_LC2_B21 &  _LC4_B21
         # !en &  _LC5_B21;

-- Node name is '|CNT10:6|:10' = '|CNT10:6|tem3' 
-- Equation name is '_LC8_B21', type is buried 
_LC8_B21 = DFFE( _EQ046,  _LC3_B16, GLOBAL(!clr),  VCC,  VCC);
  _EQ046 = !_LC2_B21 & !_LC6_B21 &  _LC8_B21
         #  en & !_LC2_B21 &  _LC6_B21 & !_LC8_B21
         # !en &  _LC8_B21;

-- Node name is '|CNT10:6|:8' 
-- Equation name is '_LC1_B21', type is buried 
_LC1_B21 = DFFE( _EQ047,  _LC3_B16,  VCC,  VCC, !_LC4_A16);
  _EQ047 =  en &  _LC2_B21
         # !en &  _LC1_B21;

-- Node name is '|CNT10:6|:51' 
-- Equation name is '_LC2_B21', type is buried 
_LC2_B21 = LCELL( _EQ048);
  _EQ048 = !_LC3_B21 & !_LC5_B21 &  _LC7_B21 &  _LC8_B21;

-- Node name is '|CNT10:7|LPM_ADD_SUB:83|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C22', type is buried 
_LC8_C22 = LCELL( _EQ049);
  _EQ049 =  _LC1_C22 &  _LC5_C22 &  _LC6_C22;

-- Node name is '|CNT10:7|LPM_ADD_SUB:83|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C22', type is buried 
_LC7_C22 = LCELL( _EQ050);
  _EQ050 =  _LC1_C22 & !_LC6_C22
         #  _LC1_C22 & !_LC5_C22
         # !_LC1_C22 &  _LC5_C22 &  _LC6_C22;

-- Node name is '|CNT10:7|:13' = '|CNT10:7|tem0' 
-- Equation name is '_LC5_C22', type is buried 
_LC5_C22 = DFFE( _EQ051,  _LC1_B21, GLOBAL(!clr),  VCC,  VCC);
  _EQ051 = !en &  _LC5_C22
         #  en & !_LC5_C22;

-- Node name is '|CNT10:7|:12' = '|CNT10:7|tem1' 
-- Equation name is '_LC6_C22', type is buried 
_LC6_C22 = DFFE( _EQ052,  _LC1_B21, GLOBAL(!clr),  VCC,  VCC);
  _EQ052 = !_LC4_C22 & !_LC5_C22 &  _LC6_C22
         #  en & !_LC4_C22 &  _LC5_C22 & !_LC6_C22
         # !en &  _LC6_C22;

-- Node name is '|CNT10:7|:11' = '|CNT10:7|tem2' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = DFFE( _EQ053,  _LC1_B21, GLOBAL(!clr),  VCC,  VCC);
  _EQ053 =  en & !_LC4_C22 &  _LC7_C22
         # !en &  _LC1_C22;

-- Node name is '|CNT10:7|:10' = '|CNT10:7|tem3' 
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = DFFE( _EQ054,  _LC1_B21, GLOBAL(!clr),  VCC,  VCC);
  _EQ054 =  _LC2_C22 & !_LC4_C22 & !_LC8_C22
         #  en & !_LC2_C22 & !_LC4_C22 &  _LC8_C22
         # !en &  _LC2_C22;

-- Node name is '|CNT10:7|:8' 
-- Equation name is '_LC3_C22', type is buried 
_LC3_C22 = DFFE( _EQ055,  _LC1_B21,  VCC,  VCC, !_LC4_A16);
  _EQ055 =  en &  _LC4_C22
         # !en &  _LC3_C22;

-- Node name is '|CNT10:7|:51' 
-- Equation name is '_LC4_C22', type is buried 
_LC4_C22 = LCELL( _EQ056);
  _EQ056 = !_LC1_C22 &  _LC2_C22 &  _LC5_C22 & !_LC6_C22;

-- Node name is '|CNT10:8|LPM_ADD_SUB:83|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = LCELL( _EQ057);
  _EQ057 =  _LC1_C4 &  _LC2_C4 &  _LC6_C4;

-- Node name is '|CNT10:8|LPM_ADD_SUB:83|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C4', type is buried 
_LC7_C4  = LCELL( _EQ058);
  _EQ058 =  _LC2_C4 & !_LC6_C4
         # !_LC1_C4 &  _LC2_C4
         #  _LC1_C4 & !_LC2_C4 &  _LC6_C4;

-- Node name is '|CNT10:8|:13' = '|CNT10:8|tem0' 
-- Equation name is '_LC1_C4', type is buried 
_LC1_C4  = DFFE( _EQ059,  _LC3_C22, GLOBAL(!clr),  VCC,  VCC);
  _EQ059 = !en &  _LC1_C4
         #  en & !_LC1_C4;

-- Node name is '|CNT10:8|:12' = '|CNT10:8|tem1' 
-- Equation name is '_LC6_C4', type is buried 
_LC6_C4  = DFFE( _EQ060,  _LC3_C22, GLOBAL(!clr),  VCC,  VCC);
  _EQ060 = !_LC1_C4 & !_LC4_C4 &  _LC6_C4
         #  en &  _LC1_C4 & !_LC4_C4 & !_LC6_C4
         # !en &  _LC6_C4;

-- Node name is '|CNT10:8|:11' = '|CNT10:8|tem2' 
-- Equation name is '_LC2_C4', type is buried 
_LC2_C4  = DFFE( _EQ061,  _LC3_C22, GLOBAL(!clr),  VCC,  VCC);
  _EQ061 =  en & !_LC4_C4 &  _LC7_C4
         # !en &  _LC2_C4;

-- Node name is '|CNT10:8|:10' = '|CNT10:8|tem3' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = DFFE( _EQ062,  _LC3_C22, GLOBAL(!clr),  VCC,  VCC);
  _EQ062 = !_LC4_C4 &  _LC5_C4 & !_LC8_C4
         #  en & !_LC4_C4 & !_LC5_C4 &  _LC8_C4
         # !en &  _LC5_C4;

-- Node name is '|CNT10:8|:8' 
-- Equation name is '_LC3_C4', type is buried 
_LC3_C4  = DFFE( _EQ063,  _LC3_C22,  VCC,  VCC, !_LC4_A16);
  _EQ063 =  en &  _LC4_C4
         # !en &  _LC3_C4;

-- Node name is '|CNT10:8|:51' 
-- Equation name is '_LC4_C4', type is buried 
!_LC4_C4 = _LC4_C4~NOT;
_LC4_C4~NOT = LCELL( _EQ064);
  _EQ064 =  _LC2_C4
         #  _LC6_C4
         # !_LC5_C4
         # !_LC1_C4;



Project Information                                    e:\eda\last\cnt10_8.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 29,992K