cnt10_8.rpt
来自「本程序完整的实现了数字频率计的常用功能。并对通常数字频率计的常见问题进行了改进。」· RPT 代码 · 共 1,118 行 · 第 1/4 页
RPT
1,118 行
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
7 - - - 03 OUTPUT 0 1 0 0 cin
70 - - A -- OUTPUT 0 1 0 0 sd0
5 - - - 05 OUTPUT 0 1 0 0 sd1
35 - - - 06 OUTPUT 0 1 0 0 sd2
60 - - C -- OUTPUT 0 1 0 0 sd3
19 - - A -- OUTPUT 0 1 0 0 sd4
69 - - A -- OUTPUT 0 1 0 0 sd5
3 - - - 12 OUTPUT 0 1 0 0 sd6
39 - - - 11 OUTPUT 0 1 0 0 sd7
17 - - A -- OUTPUT 0 1 0 0 sd8
71 - - A -- OUTPUT 0 1 0 0 sd9
38 - - - 10 OUTPUT 0 1 0 0 sd10
37 - - - 09 OUTPUT 0 1 0 0 sd11
73 - - A -- OUTPUT 0 1 0 0 sd12
83 - - - 13 OUTPUT 0 1 0 0 sd13
72 - - A -- OUTPUT 0 1 0 0 sd14
47 - - - 14 OUTPUT 0 1 0 0 sd15
67 - - B -- OUTPUT 0 1 0 0 sd16
22 - - B -- OUTPUT 0 1 0 0 sd17
24 - - B -- OUTPUT 0 1 0 0 sd18
23 - - B -- OUTPUT 0 1 0 0 sd19
64 - - B -- OUTPUT 0 1 0 0 sd20
66 - - B -- OUTPUT 0 1 0 0 sd21
65 - - B -- OUTPUT 0 1 0 0 sd22
25 - - B -- OUTPUT 0 1 0 0 sd23
59 - - C -- OUTPUT 0 1 0 0 sd24
58 - - C -- OUTPUT 0 1 0 0 sd25
62 - - C -- OUTPUT 0 1 0 0 sd26
61 - - C -- OUTPUT 0 1 0 0 sd27
27 - - C -- OUTPUT 0 1 0 0 sd28
30 - - C -- OUTPUT 0 1 0 0 sd29
28 - - C -- OUTPUT 0 1 0 0 sd30
29 - - C -- OUTPUT 0 1 0 0 sd31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\last\cnt10_8.rpt
cnt10_8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 16 SOFT s ! 1 0 0 8 clr~1
- 7 - A 05 AND2 0 3 0 1 |CNT10:1|LPM_ADD_SUB:83|addcore:adder|:63
- 2 - A 05 OR2 0 3 0 1 |CNT10:1|LPM_ADD_SUB:83|addcore:adder|:76
- 1 - A 11 DFFE + 1 2 0 5 |CNT10:1|:8
- 4 - A 05 DFFE + 1 2 1 1 |CNT10:1|tem3 (|CNT10:1|:10)
- 6 - A 05 DFFE + 1 2 1 3 |CNT10:1|tem2 (|CNT10:1|:11)
- 1 - A 05 DFFE + 1 2 1 3 |CNT10:1|tem1 (|CNT10:1|:12)
- 5 - A 05 DFFE + 1 0 1 4 |CNT10:1|tem0 (|CNT10:1|:13)
- 3 - A 05 AND2 0 4 0 4 |CNT10:1|:51
- 6 - A 11 AND2 0 3 0 1 |CNT10:2|LPM_ADD_SUB:83|addcore:adder|:63
- 5 - A 11 OR2 0 3 0 1 |CNT10:2|LPM_ADD_SUB:83|addcore:adder|:76
- 5 - A 10 DFFE 1 3 0 5 |CNT10:2|:8
- 3 - A 11 DFFE 1 3 1 1 |CNT10:2|tem3 (|CNT10:2|:10)
- 4 - A 11 DFFE 1 3 1 3 |CNT10:2|tem2 (|CNT10:2|:11)
- 8 - A 11 DFFE 1 3 1 3 |CNT10:2|tem1 (|CNT10:2|:12)
- 7 - A 11 DFFE 1 1 1 4 |CNT10:2|tem0 (|CNT10:2|:13)
- 2 - A 11 AND2 0 4 0 4 |CNT10:2|:51
- 8 - A 10 AND2 0 3 0 1 |CNT10:3|LPM_ADD_SUB:83|addcore:adder|:63
- 7 - A 10 OR2 0 3 0 1 |CNT10:3|LPM_ADD_SUB:83|addcore:adder|:76
- 2 - A 13 DFFE 1 3 0 5 |CNT10:3|:8
- 4 - A 10 DFFE 1 3 1 1 |CNT10:3|tem3 (|CNT10:3|:10)
- 6 - A 10 DFFE 1 3 1 3 |CNT10:3|tem2 (|CNT10:3|:11)
- 3 - A 10 DFFE 1 3 1 3 |CNT10:3|tem1 (|CNT10:3|:12)
- 2 - A 10 DFFE 1 1 1 4 |CNT10:3|tem0 (|CNT10:3|:13)
- 1 - A 10 AND2 0 4 0 4 |CNT10:3|:51
- 7 - A 13 AND2 0 3 0 1 |CNT10:4|LPM_ADD_SUB:83|addcore:adder|:63
- 6 - A 13 OR2 0 3 0 1 |CNT10:4|LPM_ADD_SUB:83|addcore:adder|:76
- 1 - A 16 DFFE 1 3 0 5 |CNT10:4|:8
- 8 - A 13 DFFE 1 3 1 1 |CNT10:4|tem3 (|CNT10:4|:10)
- 3 - A 13 DFFE 1 3 1 3 |CNT10:4|tem2 (|CNT10:4|:11)
- 4 - A 13 DFFE 1 3 1 3 |CNT10:4|tem1 (|CNT10:4|:12)
- 1 - A 13 DFFE 1 1 1 4 |CNT10:4|tem0 (|CNT10:4|:13)
- 5 - A 13 AND2 0 4 0 4 |CNT10:4|:51
- 8 - B 16 AND2 0 3 0 1 |CNT10:5|LPM_ADD_SUB:83|addcore:adder|:63
- 7 - B 16 OR2 0 3 0 1 |CNT10:5|LPM_ADD_SUB:83|addcore:adder|:76
- 3 - B 16 DFFE 1 3 0 5 |CNT10:5|:8
- 4 - B 16 DFFE 1 3 1 1 |CNT10:5|tem3 (|CNT10:5|:10)
- 6 - B 16 DFFE 1 3 1 3 |CNT10:5|tem2 (|CNT10:5|:11)
- 2 - B 16 DFFE 1 3 1 3 |CNT10:5|tem1 (|CNT10:5|:12)
- 1 - B 16 DFFE 1 1 1 4 |CNT10:5|tem0 (|CNT10:5|:13)
- 5 - B 16 AND2 0 4 0 4 |CNT10:5|:51
- 6 - B 21 AND2 0 3 0 1 |CNT10:6|LPM_ADD_SUB:83|addcore:adder|:63
- 4 - B 21 OR2 0 3 0 1 |CNT10:6|LPM_ADD_SUB:83|addcore:adder|:76
- 1 - B 21 DFFE 1 3 0 5 |CNT10:6|:8
- 8 - B 21 DFFE 1 3 1 1 |CNT10:6|tem3 (|CNT10:6|:10)
- 5 - B 21 DFFE 1 3 1 3 |CNT10:6|tem2 (|CNT10:6|:11)
- 3 - B 21 DFFE 1 3 1 3 |CNT10:6|tem1 (|CNT10:6|:12)
- 7 - B 21 DFFE 1 1 1 4 |CNT10:6|tem0 (|CNT10:6|:13)
- 2 - B 21 AND2 0 4 0 4 |CNT10:6|:51
- 8 - C 22 AND2 0 3 0 1 |CNT10:7|LPM_ADD_SUB:83|addcore:adder|:63
- 7 - C 22 OR2 0 3 0 1 |CNT10:7|LPM_ADD_SUB:83|addcore:adder|:76
- 3 - C 22 DFFE 1 3 0 5 |CNT10:7|:8
- 2 - C 22 DFFE 1 3 1 1 |CNT10:7|tem3 (|CNT10:7|:10)
- 1 - C 22 DFFE 1 3 1 3 |CNT10:7|tem2 (|CNT10:7|:11)
- 6 - C 22 DFFE 1 3 1 3 |CNT10:7|tem1 (|CNT10:7|:12)
- 5 - C 22 DFFE 1 1 1 4 |CNT10:7|tem0 (|CNT10:7|:13)
- 4 - C 22 AND2 0 4 0 4 |CNT10:7|:51
- 8 - C 04 AND2 0 3 0 1 |CNT10:8|LPM_ADD_SUB:83|addcore:adder|:63
- 7 - C 04 OR2 0 3 0 1 |CNT10:8|LPM_ADD_SUB:83|addcore:adder|:76
- 3 - C 04 DFFE 1 3 1 0 |CNT10:8|:8
- 5 - C 04 DFFE 1 3 1 1 |CNT10:8|tem3 (|CNT10:8|:10)
- 2 - C 04 DFFE 1 3 1 3 |CNT10:8|tem2 (|CNT10:8|:11)
- 6 - C 04 DFFE 1 3 1 3 |CNT10:8|tem1 (|CNT10:8|:12)
- 1 - C 04 DFFE 1 1 1 4 |CNT10:8|tem0 (|CNT10:8|:13)
- 4 - C 04 OR2 ! 0 4 0 4 |CNT10:8|:51
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\last\cnt10_8.rpt
cnt10_8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 5/ 48( 10%) 3/ 48( 6%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 6/ 96( 6%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 5/ 96( 5%) 3/ 48( 6%) 4/ 48( 8%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\last\cnt10_8.rpt
cnt10_8
** CLOCK SIGNALS **
Type Fan-out Name
DFF 6 |CNT10:1|:8
DFF 6 |CNT10:2|:8
DFF 6 |CNT10:3|:8
DFF 6 |CNT10:4|:8
DFF 6 |CNT10:5|:8
DFF 6 |CNT10:6|:8
DFF 6 |CNT10:7|:8
INPUT 5 fsin
Device-Specific Information: e:\eda\last\cnt10_8.rpt
cnt10_8
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 33 clr
Device-Specific Information: e:\eda\last\cnt10_8.rpt
cnt10_8
** EQUATIONS **
clr : INPUT;
en : INPUT;
fsin : INPUT;
-- Node name is 'cin'
-- Equation name is 'cin', type is output
cin = _LC3_C4;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC4_A16, type is buried.
-- synthesized logic cell
!_LC4_A16 = _LC4_A16~NOT;
_LC4_A16~NOT = LCELL(!clr);
-- Node name is 'sd0'
-- Equation name is 'sd0', type is output
sd0 = _LC5_A5;
-- Node name is 'sd1'
-- Equation name is 'sd1', type is output
sd1 = _LC1_A5;
-- Node name is 'sd2'
-- Equation name is 'sd2', type is output
sd2 = _LC6_A5;
-- Node name is 'sd3'
-- Equation name is 'sd3', type is output
sd3 = _LC4_A5;
-- Node name is 'sd4'
-- Equation name is 'sd4', type is output
sd4 = _LC7_A11;
-- Node name is 'sd5'
-- Equation name is 'sd5', type is output
sd5 = _LC8_A11;
-- Node name is 'sd6'
-- Equation name is 'sd6', type is output
sd6 = _LC4_A11;
-- Node name is 'sd7'
-- Equation name is 'sd7', type is output
sd7 = _LC3_A11;
-- Node name is 'sd8'
-- Equation name is 'sd8', type is output
sd8 = _LC2_A10;
-- Node name is 'sd9'
-- Equation name is 'sd9', type is output
sd9 = _LC3_A10;
-- Node name is 'sd10'
-- Equation name is 'sd10', type is output
sd10 = _LC6_A10;
-- Node name is 'sd11'
-- Equation name is 'sd11', type is output
sd11 = _LC4_A10;
-- Node name is 'sd12'
-- Equation name is 'sd12', type is output
sd12 = _LC1_A13;
-- Node name is 'sd13'
-- Equation name is 'sd13', type is output
sd13 = _LC4_A13;
-- Node name is 'sd14'
-- Equation name is 'sd14', type is output
sd14 = _LC3_A13;
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