reg32.vhd

来自「本程序完整的实现了数字频率计的常用功能。并对通常数字频率计的常见问题进行了改进。」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
 port(load:in std_logic;
      datain:in std_logic_vector(31 downto 0);
      dataout:out std_logic_vector(31 downto 0));
end entity;
architecture art of reg32 is
  begin
  process(load)
    begin
    if(rising_edge(load)) then
      dataout<=datain;
    end if;
  end process;
end art;