second1.vhd

来自「本程序完整的实现了数字频率计的常用功能。并对通常数字频率计的常见问题进行了改进。」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second1 is
   generic (N : integer:=9999999);
   port(clk:in std_logic;
        ci:out std_logic);
end entity second1;
architecture art of second1 is
signal tem: integer range 0 to N;
begin
  process ( clk ) 
      begin
      if(rising_edge(clk)) then
         if tem<N then
             tem<=tem+1; ci<='0';
          else tem<=0; ci<='1';
          end if;
      end if;
  end process; 
end art;