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📄 scan.rpt

📁 本程序完整的实现了数字频率计的常用功能。并对通常数字频率计的常见问题进行了改进。具有实用价值。
💻 RPT
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** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  70      -     -    A    --     OUTPUT                0    1    0    0  control0
  71      -     -    A    --     OUTPUT                0    1    0    0  control1
  73      -     -    A    --     OUTPUT                0    1    0    0  control2
  61      -     -    C    --     OUTPUT                0    1    0    0  data0
  65      -     -    B    --     OUTPUT                0    1    0    0  data1
  60      -     -    C    --     OUTPUT                0    1    0    0  data2
  58      -     -    C    --     OUTPUT                0    1    0    0  data3


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:                              e:\eda\last\scan.rpt
scan

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      1     -    A    15       DFFE   +            0    2    1    7  count2 (:41)
   -      4     -    A    15       DFFE   +            0    1    1    8  count1 (:42)
   -      8     -    A    18       DFFE   +            0    0    1    9  count0 (:43)
   -      7     -    A    15       AND2                0    3    0    4  :832
   -      2     -    A    20        OR2                2    1    0    1  :835
   -      8     -    A    15        OR2        !       0    3    0    4  :842
   -      3     -    A    20        OR2                1    2    0    1  :845
   -      6     -    A    15       AND2                0    3    0    4  :852
   -      4     -    A    20        OR2                1    2    0    1  :855
   -      5     -    A    15       AND2                0    3    0    4  :862
   -      5     -    A    20        OR2                1    2    0    1  :865
   -      1     -    A    18       AND2                0    3    0    4  :872
   -      7     -    A    20        OR2                1    2    0    1  :875
   -      3     -    A    15       AND2                0    3    0    4  :882
   -      8     -    A    20        OR2                1    2    0    1  :885
   -      2     -    A    15       AND2                0    3    0    4  :892
   -      6     -    A    20        OR2                1    2    1    0  :895
   -      1     -    A    13        OR2                2    1    0    1  :901
   -      2     -    A    23        OR2                1    2    0    1  :904
   -      3     -    A    23        OR2                1    2    0    1  :907
   -      6     -    A    23        OR2                1    2    0    1  :910
   -      7     -    A    23        OR2                1    2    0    1  :913
   -      8     -    A    23        OR2                1    2    0    1  :916
   -      4     -    A    23        OR2                1    2    1    0  :919
   -      3     -    A    13        OR2                2    1    0    1  :925
   -      4     -    A    13        OR2                1    2    0    1  :928
   -      5     -    A    13        OR2                1    2    0    1  :931
   -      6     -    A    13        OR2                1    2    0    1  :934
   -      2     -    A    13        OR2                1    2    0    1  :937
   -      1     -    A    23        OR2                1    2    0    1  :940
   -      5     -    A    23        OR2                1    2    1    0  :943
   -      1     -    A    20        OR2                2    1    0    1  :949
   -      3     -    A    18        OR2                1    2    0    1  :952
   -      4     -    A    18        OR2                1    2    0    1  :955
   -      5     -    A    18        OR2                1    2    0    1  :958
   -      6     -    A    18        OR2                1    2    0    1  :961
   -      7     -    A    18        OR2                1    2    0    1  :964
   -      2     -    A    18        OR2                1    2    1    0  :967


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                              e:\eda\last\scan.rpt
scan

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      21/ 96( 21%)     0/ 48(  0%)    20/ 48( 41%)    6/16( 37%)      3/16( 18%)     0/16(  0%)
B:       0/ 96(  0%)     0/ 48(  0%)     1/ 48(  2%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     3/ 48(  6%)    0/16(  0%)      3/16( 18%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
03:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
10:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
14:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
15:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
17:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
19:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
20:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      3/24( 12%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                              e:\eda\last\scan.rpt
scan

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        3         clk


Device-Specific Information:                              e:\eda\last\scan.rpt
scan

** EQUATIONS **

clk      : INPUT;
indata0  : INPUT;
indata1  : INPUT;
indata2  : INPUT;
indata3  : INPUT;
indata4  : INPUT;
indata5  : INPUT;
indata6  : INPUT;
indata7  : INPUT;
indata8  : INPUT;
indata9  : INPUT;
indata10 : INPUT;
indata11 : INPUT;
indata12 : INPUT;
indata13 : INPUT;
indata14 : INPUT;
indata15 : INPUT;
indata16 : INPUT;
indata17 : INPUT;
indata18 : INPUT;
indata19 : INPUT;
indata20 : INPUT;
indata21 : INPUT;
indata22 : INPUT;
indata23 : INPUT;
indata24 : INPUT;
indata25 : INPUT;
indata26 : INPUT;
indata27 : INPUT;
indata28 : INPUT;
indata29 : INPUT;
indata30 : INPUT;
indata31 : INPUT;

-- Node name is 'control0' 
-- Equation name is 'control0', type is output 
control0 =  count0;

-- Node name is 'control1' 
-- Equation name is 'control1', type is output 
control1 =  count1;

-- Node name is 'control2' 
-- Equation name is 'control2', type is output 
control2 =  count2;

-- Node name is ':43' = 'count0' 
-- Equation name is 'count0', location is LC8_A18, type is buried.
count0   = DFFE(!count0, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':42' = 'count1' 
-- Equation name is 'count1', location is LC4_A15, type is buried.
count1   = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !count0 &  count1
         #  count0 & !count1;

-- Node name is ':41' = 'count2' 
-- Equation name is 'count2', location is LC1_A15, type is buried.
count2   = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  count0 &  count1 & !count2
         # !count1 &  count2
         # !count0 &  count2;

-- Node name is 'data0' 
-- Equation name is 'data0', type is output 
data0    =  _LC2_A18;

-- Node name is 'data1' 
-- Equation name is 'data1', type is output 
data1    =  _LC5_A23;

-- Node name is 'data2' 
-- Equation name is 'data2', type is output 
data2    =  _LC4_A23;

-- Node name is 'data3' 
-- Equation name is 'data3', type is output 
data3    =  _LC6_A20;

-- Node name is ':832' 
-- Equation name is '_LC7_A15', type is buried 
_LC7_A15 = LCELL( _EQ003);
  _EQ003 = !count0 &  count1 &  count2;

-- Node name is ':835' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ004);
  _EQ004 =  indata31 & !_LC7_A15
         #  indata27 &  _LC7_A15;

-- Node name is ':842' 
-- Equation name is '_LC8_A15', type is buried 
!_LC8_A15 = _LC8_A15~NOT;
_LC8_A15~NOT = LCELL( _EQ005);
  _EQ005 =  count1
         # !count0
         # !count2;

-- Node name is ':845' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ006);
  _EQ006 =  indata23 &  _LC8_A15
         #  _LC2_A20 & !_LC8_A15;

-- Node name is ':852' 
-- Equation name is '_LC6_A15', type is buried 
_LC6_A15 = LCELL( _EQ007);
  _EQ007 = !count0 & !count1 &  count2;

-- Node name is ':855' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ008);
  _EQ008 =  _LC3_A20 & !_LC6_A15
         #  indata19 &  _LC6_A15;

-- Node name is ':862' 
-- Equation name is '_LC5_A15', type is buried 
_LC5_A15 = LCELL( _EQ009);

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