📄 ledshow.rpt
字号:
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\last\ledshow.rpt
ledshow
** EQUATIONS **
data0 : INPUT;
data1 : INPUT;
data2 : INPUT;
data3 : INPUT;
-- Node name is 'dout0'
-- Equation name is 'dout0', type is output
dout0 = _LC1_B24;
-- Node name is 'dout1'
-- Equation name is 'dout1', type is output
dout1 = _LC8_B8;
-- Node name is 'dout2'
-- Equation name is 'dout2', type is output
dout2 = _LC6_B24;
-- Node name is 'dout3'
-- Equation name is 'dout3', type is output
dout3 = _LC3_B24;
-- Node name is 'dout4'
-- Equation name is 'dout4', type is output
dout4 = _LC1_B8;
-- Node name is 'dout5'
-- Equation name is 'dout5', type is output
dout5 = _LC2_B8;
-- Node name is 'dout6'
-- Equation name is 'dout6', type is output
dout6 = _LC1_C4;
-- Node name is ':81'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ001);
_EQ001 = !data0 & !data1 & data2 & !data3;
-- Node name is ':105'
-- Equation name is '_LC7_B24', type is buried
!_LC7_B24 = _LC7_B24~NOT;
_LC7_B24~NOT = LCELL( _EQ002);
_EQ002 = !data1
# data3
# data0
# data2;
-- Node name is ':117'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = LCELL( _EQ003);
_EQ003 = data0 & !data1 & !data2 & !data3;
-- Node name is ':129'
-- Equation name is '_LC3_B8', type is buried
_LC3_B8 = LCELL( _EQ004);
_EQ004 = !data0 & !data1 & !data2 & !data3;
-- Node name is '~134~1'
-- Equation name is '~134~1', location is LC4_B24, type is buried.
-- synthesized logic cell
!_LC4_B24 = _LC4_B24~NOT;
_LC4_B24~NOT = LCELL( _EQ005);
_EQ005 = _LC2_B24
# _LC3_B8;
-- Node name is ':134'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ006);
_EQ006 = !data0 & data2 & !data3
# !data1 & data2 & !data3
# !data0 & data1 & !data3
# data1 & !data2 & !data3
# !data1 & !data2 & data3;
-- Node name is ':165'
-- Equation name is '_LC2_B8', type is buried
_LC2_B8 = LCELL( _EQ007);
_EQ007 = _LC5_B8 & _LC7_B8
# _LC4_B8 & _LC5_B8
# _LC3_B8;
-- Node name is '~167~1'
-- Equation name is '~167~1', location is LC5_B8, type is buried.
-- synthesized logic cell
!_LC5_B8 = _LC5_B8~NOT;
_LC5_B8~NOT = LCELL( _EQ008);
_EQ008 = data1 & !data2 & !data3
# data0 & !data2 & !data3;
-- Node name is '~194~1'
-- Equation name is '~194~1', location is LC5_B24, type is buried.
-- synthesized logic cell
!_LC5_B24 = _LC5_B24~NOT;
_LC5_B24~NOT = LCELL( _EQ009);
_EQ009 = !data0 & !data1 & data2 & !data3
# data0 & data1 & !data2 & !data3;
-- Node name is ':198'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = LCELL( _EQ010);
_EQ010 = !data0 & !data2 & !data3
# !data0 & !data1 & !data2
# !data0 & data1 & !data3;
-- Node name is ':216'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = LCELL( _EQ011);
_EQ011 = !data1 & !data2 & data3
# data0 & !data1 & data2 & !data3
# !data0 & data1 & data2 & !data3;
-- Node name is ':231'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ012);
_EQ012 = !data0 & !data2 & !data3
# data1 & !data2 & !data3
# !data1 & !data2 & data3
# !data0 & !data1 & !data2
# !data0 & data1 & !data3
# data0 & !data1 & data2 & !data3;
-- Node name is ':264'
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = LCELL( _EQ013);
_EQ013 = !_LC4_B24
# !_LC5_B24 & !_LC7_B24
# !_LC7_B24 & _LC8_B24;
-- Node name is ':287'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = LCELL( _EQ014);
_EQ014 = !data1 & !data2 & data3
# data0 & data1 & data2 & !data3;
-- Node name is ':297'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = LCELL( _EQ015);
_EQ015 = _LC3_B8
# _LC4_B8
# !_LC5_B8
# _LC6_B8;
-- Node name is ':315'
-- Equation name is '_LC8_B24', type is buried
_LC8_B24 = LCELL( _EQ016);
_EQ016 = data0 & data2 & !data3
# !data1 & !data2 & data3
# data1 & data2 & !data3;
-- Node name is ':330'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = LCELL( _EQ017);
_EQ017 = !data0 & !data2 & !data3
# data0 & data2 & !data3
# !data1 & !data2 & data3
# !data0 & !data1 & !data2
# data1 & !data3;
Project Information e:\eda\last\ledshow.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,399K
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