📄 reg32.rpt
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& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\eda\last\reg32.rpt
reg32
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
8 - - A -- OUTPUT 0 1 0 0 dataout0
99 - - A -- OUTPUT 0 1 0 0 dataout1
21 - - B -- OUTPUT 0 1 0 0 dataout2
117 - - - 06 OUTPUT 0 1 0 0 dataout3
91 - - B -- OUTPUT 0 1 0 0 dataout4
13 - - A -- OUTPUT 0 1 0 0 dataout5
33 - - C -- OUTPUT 0 1 0 0 dataout6
30 - - C -- OUTPUT 0 1 0 0 dataout7
79 - - C -- OUTPUT 0 1 0 0 dataout8
46 - - - 17 OUTPUT 0 1 0 0 dataout9
135 - - - 18 OUTPUT 0 1 0 0 dataout10
90 - - B -- OUTPUT 0 1 0 0 dataout11
26 - - C -- OUTPUT 0 1 0 0 dataout12
7 - - A -- OUTPUT 0 1 0 0 dataout13
82 - - C -- OUTPUT 0 1 0 0 dataout14
95 - - A -- OUTPUT 0 1 0 0 dataout15
29 - - C -- OUTPUT 0 1 0 0 dataout16
17 - - B -- OUTPUT 0 1 0 0 dataout17
112 - - - 03 OUTPUT 0 1 0 0 dataout18
88 - - B -- OUTPUT 0 1 0 0 dataout19
64 - - - 10 OUTPUT 0 1 0 0 dataout20
101 - - A -- OUTPUT 0 1 0 0 dataout21
89 - - B -- OUTPUT 0 1 0 0 dataout22
100 - - A -- OUTPUT 0 1 0 0 dataout23
28 - - C -- OUTPUT 0 1 0 0 dataout24
23 - - B -- OUTPUT 0 1 0 0 dataout25
11 - - A -- OUTPUT 0 1 0 0 dataout26
92 - - B -- OUTPUT 0 1 0 0 dataout27
27 - - C -- OUTPUT 0 1 0 0 dataout28
10 - - A -- OUTPUT 0 1 0 0 dataout29
98 - - A -- OUTPUT 0 1 0 0 dataout30
83 - - C -- OUTPUT 0 1 0 0 dataout31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\last\reg32.rpt
reg32
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 07 DFFE + 1 0 1 0 :34
- 5 - A 11 DFFE + 1 0 1 0 :36
- 4 - A 17 DFFE + 1 0 1 0 :38
- 2 - C 19 DFFE + 1 0 1 0 :40
- 1 - B 03 DFFE + 1 0 1 0 :42
- 5 - A 13 DFFE + 1 0 1 0 :44
- 7 - B 15 DFFE + 1 0 1 0 :46
- 3 - C 21 DFFE + 1 0 1 0 :48
- 2 - A 06 DFFE + 1 0 1 0 :50
- 5 - B 05 DFFE + 1 0 1 0 :52
- 2 - A 03 DFFE + 1 0 1 0 :54
- 4 - A 09 DFFE + 1 0 1 0 :56
- 6 - B 07 DFFE + 1 0 1 0 :58
- 2 - B 04 DFFE + 1 0 1 0 :60
- 1 - B 18 DFFE + 1 0 1 0 :62
- 4 - C 19 DFFE + 1 0 1 0 :64
- 8 - A 04 DFFE + 1 0 1 0 :66
- 2 - C 06 DFFE + 1 0 1 0 :68
- 1 - A 21 DFFE + 1 0 1 0 :70
- 1 - C 18 DFFE + 1 0 1 0 :72
- 4 - B 06 DFFE + 1 0 1 0 :74
- 4 - B 17 DFFE + 1 0 1 0 :76
- 2 - C 17 DFFE + 1 0 1 0 :78
- 5 - C 03 DFFE + 1 0 1 0 :80
- 5 - C 19 DFFE + 1 0 1 0 :82
- 7 - C 22 DFFE + 1 0 1 0 :84
- 7 - A 19 DFFE + 1 0 1 0 :86
- 2 - B 02 DFFE + 1 0 1 0 :88
- 8 - B 06 DFFE + 1 0 1 0 :90
- 5 - B 17 DFFE + 1 0 1 0 :92
- 4 - A 03 DFFE + 1 0 1 0 :94
- 1 - A 22 DFFE + 1 0 1 0 :96
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\last\reg32.rpt
reg32
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 6/ 48( 12%) 6/ 48( 12%) 6/16( 37%) 10/16( 62%) 0/16( 0%)
B: 8/ 96( 8%) 4/ 48( 8%) 4/ 48( 8%) 6/16( 37%) 8/16( 50%) 0/16( 0%)
C: 9/ 96( 9%) 3/ 48( 6%) 7/ 48( 14%) 5/16( 31%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\last\reg32.rpt
reg32
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 32 load
Device-Specific Information: e:\eda\last\reg32.rpt
reg32
** EQUATIONS **
datain0 : INPUT;
datain1 : INPUT;
datain2 : INPUT;
datain3 : INPUT;
datain4 : INPUT;
datain5 : INPUT;
datain6 : INPUT;
datain7 : INPUT;
datain8 : INPUT;
datain9 : INPUT;
datain10 : INPUT;
datain11 : INPUT;
datain12 : INPUT;
datain13 : INPUT;
datain14 : INPUT;
datain15 : INPUT;
datain16 : INPUT;
datain17 : INPUT;
datain18 : INPUT;
datain19 : INPUT;
datain20 : INPUT;
datain21 : INPUT;
datain22 : INPUT;
datain23 : INPUT;
datain24 : INPUT;
datain25 : INPUT;
datain26 : INPUT;
datain27 : INPUT;
datain28 : INPUT;
datain29 : INPUT;
datain30 : INPUT;
datain31 : INPUT;
load : INPUT;
-- Node name is 'dataout0'
-- Equation name is 'dataout0', type is output
dataout0 = _LC1_A22;
-- Node name is 'dataout1'
-- Equation name is 'dataout1', type is output
dataout1 = _LC4_A3;
-- Node name is 'dataout2'
-- Equation name is 'dataout2', type is output
dataout2 = _LC5_B17;
-- Node name is 'dataout3'
-- Equation name is 'dataout3', type is output
dataout3 = _LC8_B6;
-- Node name is 'dataout4'
-- Equation name is 'dataout4', type is output
dataout4 = _LC2_B2;
-- Node name is 'dataout5'
-- Equation name is 'dataout5', type is output
dataout5 = _LC7_A19;
-- Node name is 'dataout6'
-- Equation name is 'dataout6', type is output
dataout6 = _LC7_C22;
-- Node name is 'dataout7'
-- Equation name is 'dataout7', type is output
dataout7 = _LC5_C19;
-- Node name is 'dataout8'
-- Equation name is 'dataout8', type is output
dataout8 = _LC5_C3;
-- Node name is 'dataout9'
-- Equation name is 'dataout9', type is output
dataout9 = _LC2_C17;
-- Node name is 'dataout10'
-- Equation name is 'dataout10', type is output
dataout10 = _LC4_B17;
-- Node name is 'dataout11'
-- Equation name is 'dataout11', type is output
dataout11 = _LC4_B6;
-- Node name is 'dataout12'
-- Equation name is 'dataout12', type is output
dataout12 = _LC1_C18;
-- Node name is 'dataout13'
-- Equation name is 'dataout13', type is output
dataout13 = _LC1_A21;
-- Node name is 'dataout14'
-- Equation name is 'dataout14', type is output
dataout14 = _LC2_C6;
-- Node name is 'dataout15'
-- Equation name is 'dataout15', type is output
dataout15 = _LC8_A4;
-- Node name is 'dataout16'
-- Equation name is 'dataout16', type is output
dataout16 = _LC4_C19;
-- Node name is 'dataout17'
-- Equation name is 'dataout17', type is output
dataout17 = _LC1_B18;
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