📄 cnt10.rpt
字号:
- 7 - B 04 DFFE + 1 2 1 0 :8
- 1 - B 04 DFFE + 1 2 1 1 tem3 (:10)
- 3 - B 04 DFFE + 1 2 1 3 tem2 (:11)
- 8 - B 04 DFFE + 1 2 1 3 tem1 (:12)
- 5 - B 04 DFFE + 1 0 1 4 tem0 (:13)
- 2 - B 04 AND2 0 4 0 4 :51
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\last\cnt10.rpt
cnt10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\last\cnt10.rpt
cnt10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information: e:\eda\last\cnt10.rpt
cnt10
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 clr
Device-Specific Information: e:\eda\last\cnt10.rpt
cnt10
** EQUATIONS **
clk : INPUT;
clr : INPUT;
en : INPUT;
-- Node name is 'cin'
-- Equation name is 'cin', type is output
cin = _LC7_B4;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC1_B12, type is buried.
-- synthesized logic cell
!_LC1_B12 = _LC1_B12~NOT;
_LC1_B12~NOT = LCELL(!clr);
-- Node name is 'count0'
-- Equation name is 'count0', type is output
count0 = tem0;
-- Node name is 'count1'
-- Equation name is 'count1', type is output
count1 = tem1;
-- Node name is 'count2'
-- Equation name is 'count2', type is output
count2 = tem2;
-- Node name is 'count3'
-- Equation name is 'count3', type is output
count3 = tem3;
-- Node name is ':13' = 'tem0'
-- Equation name is 'tem0', location is LC5_B4, type is buried.
tem0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = !en & tem0
# en & !tem0;
-- Node name is ':12' = 'tem1'
-- Equation name is 'tem1', location is LC8_B4, type is buried.
tem1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = !_LC2_B4 & !tem0 & tem1
# en & !_LC2_B4 & tem0 & !tem1
# !en & tem1;
-- Node name is ':11' = 'tem2'
-- Equation name is 'tem2', location is LC3_B4, type is buried.
tem2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = en & !_LC2_B4 & _LC4_B4
# !en & tem2;
-- Node name is ':10' = 'tem3'
-- Equation name is 'tem3', location is LC1_B4, type is buried.
tem3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = !_LC2_B4 & !_LC6_B4 & tem3
# en & !_LC2_B4 & _LC6_B4 & !tem3
# !en & tem3;
-- Node name is '|LPM_ADD_SUB:83|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ005);
_EQ005 = tem0 & tem1 & tem2;
-- Node name is '|LPM_ADD_SUB:83|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = LCELL( _EQ006);
_EQ006 = !tem1 & tem2
# !tem0 & tem2
# tem0 & tem1 & !tem2;
-- Node name is ':8'
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, !_LC1_B12);
_EQ007 = en & _LC2_B4
# !en & _LC7_B4;
-- Node name is ':51'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = LCELL( _EQ008);
_EQ008 = tem0 & !tem1 & !tem2 & tem3;
Project Information e:\eda\last\cnt10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 28,901K
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