databuffer.tan.rpt

buffer for in/out data.

; Worst-case tsu               ; N/A   ; None          ; 0.585 ns                                       ; SW[5]                                                                                                                          ; data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 ; --         ; CLOCK_50 ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 11.400 ns                                      ; data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg7 ; LEDG[5]                                                                                                                        ; CLOCK_50   ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 6.016 ns                                       ; CLOCK_50                                                                                                                       ; LEDR[0]                                                                                                                        ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.353 ns                                       ; SW[2]                                                                                                                          ; data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 ; --         ; CLOCK_50 ; 0            ;
; Clock Setup: 'CLOCK_50'      ; N/A   ; None          ; Restricted to 195.01 MHz ( period = 5.128 ns ) ; COUNT[0]                                                                                                                       ; data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 ; CLOCK_50   ; CLOCK_50 ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                                                                ;                                                                                                                                ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C20F484C7       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+