databuffer.map.rpt

buffer for in/out data.

; INDATA_REG_B                       ; CLOCK1               ; Untyped                  ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                  ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                  ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                  ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                  ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                  ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                  ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                  ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                  ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                  ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                  ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                  ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                  ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                  ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                  ;
; BYTE_SIZE                          ; 8                    ; Untyped                  ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                  ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                  ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                  ;
; INIT_FILE                          ; UNUSED               ; Untyped                  ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                  ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                  ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                  ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                  ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                  ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                  ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                  ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                  ;
; ENABLE_ECC                         ; FALSE                ; Untyped                  ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                  ;
; CBXI_PARAMETER                     ; altsyncram_3te1      ; Untyped                  ;
+------------------------------------+----------------------+--------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sun Nov 02 21:20:57 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DATABUFFER -c DATABUFFER
Info: Found 2 design units, including 1 entities, in source file ../ClockGen.vhd
    Info: Found design unit 1: ClockGen-behav
    Info: Found entity 1: ClockGen
Info: Found 2 design units, including 1 entities, in source file BUFFER.vhd
    Info: Found design unit 1: data_buffer-RTL
    Info: Found entity 1: data_buffer
Info: Found 2 design units, including 1 entities, in source file DATABUFFER.vhd
    Info: Found design unit 1: DATABUFFER-struct
    Info: Found entity 1: DATABUFFER
Info: Elaborating entity "DATABUFFER" for the top level hierarchy
Warning (10034): Output port "LEDR[9]" at DATABUFFER.vhd(10) has no driver
Warning (10034): Output port "LEDR[8]" at DATABUFFER.vhd(10) has no driver
Warning (10034): Output port "LEDR[7]" at DATABUFFER.vhd(10) has no driver
Warning (10034): Output port "LEDR[6]" at DATABUFFER.vhd(10) has no driver
Warning (10034): Output port "LEDR[5]" at DATABUFFER.vhd(10) has no driver
Warning (10034): Output port "LEDR[4]" at DATABUFFER.vhd(10) has no driver
Warning (10034): Output port "LEDR[3]" at DATABUFFER.vhd(10) has no driver
Warning (10034): Output port "LEDR[2]" at DATABUFFER.vhd(10) has no driver
Warning (10034): Output port "LEDR[1]" at DATABUFFER.vhd(10) has no driver
Info: Elaborating entity "ClockGen" for hierarchy "ClockGen:SI"
Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(18): used explicit default value for signal "count100K" because signal was never assigned a value
Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(19): used explicit default value for signal "count10K" because signal was never assigned a value
Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(20): used explicit default value for signal "count1K" because signal was never assigned a value
Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(21): used explicit default value for signal "count100" because signal was never assigned a value
Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(22): used explicit default value for signal "count10" because signal was never assigned a value
Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(23): used explicit default value for signal "count1" because signal was never assigned a value
Warning (10492): VHDL Process Statement warning at ClockGen.vhd(34): signal "count1M" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ClockGen.vhd(51): signal "count100K" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ClockGen.vhd(67): signal "count10K" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ClockGen.vhd(83): signal "count1K" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ClockGen.vhd(99): signal "count100" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ClockGen.vhd(115): signal "count10" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ClockGen.vhd(131): signal "count1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "data_buffer" for hierarchy "data_buffer:b"
Info: Duplicate registers merged to single register
    Info (13360): Duplicate register "DATA[0]" merged to single register "COUNT[0]", power-up level changed
    Info (13360): Duplicate register "ADDRESS[0]" merged to single register "COUNT[0]", power-up level changed
    Info (13350): Duplicate register "ADDRESS[1]" merged to single register "DATA[1]"
    Info (13350): Duplicate register "ADDRESS[2]" merged to single register "DATA[2]"
    Info (13350): Duplicate register "ADDRESS[3]" merged to single register "DATA[3]"
    Info (13350): Duplicate register "ADDRESS[4]" merged to single register "DATA[4]"
    Info (13350): Duplicate register "ADDRESS[5]" merged to single register "DATA[5]"
    Info (13350): Duplicate register "ADDRESS[6]" merged to single register "DATA[6]"
    Info (13350): Duplicate register "ADDRESS[7]" merged to single register "DATA[7]"
Warning: Inferred dual-clock RAM node "data_buffer:b|data~17" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altsyncram megafunction from the following design logic: "data_buffer:b|data~17" 
        Info: Parameter OPERATION_MODE set to DUAL_PORT
        Info: Parameter WIDTH_A set to 8
        Info: Parameter WIDTHAD_A set to 8
        Info: Parameter NUMWORDS_A set to 256
        Info: Parameter WIDTH_B set to 8
        Info: Parameter WIDTHAD_B set to 8
        Info: Parameter NUMWORDS_B set to 256
        Info: Parameter ADDRESS_ACLR_A set to NONE
        Info: Parameter OUTDATA_REG_B set to UNREGISTERED
        Info: Parameter ADDRESS_ACLR_B set to NONE
        Info: Parameter OUTDATA_ACLR_B set to NONE
        Info: Parameter ADDRESS_REG_B set to CLOCK1
        Info: Parameter INDATA_ACLR_A set to NONE
        Info: Parameter WRCONTROL_ACLR_A set to NONE
        Info: Parameter RAM_BLOCK_TYPE set to AUTO
Info: Elaborated megafunction instantiation "data_buffer:b|altsyncram:data_rtl_0"
Info: Instantiated megafunction "data_buffer:b|altsyncram:data_rtl_0" with the following parameter:
    Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
    Info: Parameter "WIDTH_A" = "8"
    Info: Parameter "WIDTHAD_A" = "8"
    Info: Parameter "NUMWORDS_A" = "256"
    Info: Parameter "WIDTH_B" = "8"
    Info: Parameter "WIDTHAD_B" = "8"
    Info: Parameter "NUMWORDS_B" = "256"
    Info: Parameter "ADDRESS_ACLR_A" = "NONE"
    Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
    Info: Parameter "ADDRESS_ACLR_B" = "NONE"
    Info: Parameter "OUTDATA_ACLR_B" = "NONE"
    Info: Parameter "ADDRESS_REG_B" = "CLOCK1"
    Info: Parameter "INDATA_ACLR_A" = "NONE"
    Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info: Parameter "RAM_BLOCK_TYPE" = "AUTO"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3te1.tdf
    Info: Found entity 1: altsyncram_3te1
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_6gi1.tdf
    Info: Found entity 1: altsyncram_6gi1
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "LEDR[1]" is stuck at GND
    Warning (13410): Pin "LEDR[2]" is stuck at GND
    Warning (13410): Pin "LEDR[3]" is stuck at GND
    Warning (13410): Pin "LEDR[4]" is stuck at GND
    Warning (13410): Pin "LEDR[5]" is stuck at GND
    Warning (13410): Pin "LEDR[6]" is stuck at GND
    Warning (13410): Pin "LEDR[7]" is stuck at GND
    Warning (13410): Pin "LEDR[8]" is stuck at GND
    Warning (13410): Pin "LEDR[9]" is stuck at GND
Warning: Design contains 6 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "SW[8]"
    Warning (15610): No output dependent on input pin "SW[9]"
    Warning (15610): No output dependent on input pin "KEY[0]"
    Warning (15610): No output dependent on input pin "KEY[1]"
    Warning (15610): No output dependent on input pin "KEY[2]"
    Warning (15610): No output dependent on input pin "KEY[3]"
Info: Implemented 62 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 18 output pins
    Info: Implemented 21 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 40 warnings
    Info: Peak virtual memory: 178 megabytes
    Info: Processing ended: Sun Nov 02 21:21:02 2008
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:02