prev_cmp_databuffer.map.qmsg

buffer for in/out data.

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_buffer data_buffer:b " "Info: Elaborating entity \"data_buffer\" for hierarchy \"data_buffer:b\"" {  } { { "DATABUFFER.vhd" "b" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 71 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "DATA\[0\] COUNT\[0\] " "Info (13360): Duplicate register \"DATA\[0\]\" merged to single register \"COUNT\[0\]\", power-up level changed" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 13360 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "ADDRESS\[0\] COUNT\[0\] " "Info (13360): Duplicate register \"ADDRESS\[0\]\" merged to single register \"COUNT\[0\]\", power-up level changed" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 13360 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ADDRESS\[1\] DATA\[1\] " "Info (13350): Duplicate register \"ADDRESS\[1\]\" merged to single register \"DATA\[1\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ADDRESS\[2\] DATA\[2\] " "Info (13350): Duplicate register \"ADDRESS\[2\]\" merged to single register \"DATA\[2\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ADDRESS\[3\] DATA\[3\] " "Info (13350): Duplicate register \"ADDRESS\[3\]\" merged to single register \"DATA\[3\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ADDRESS\[4\] DATA\[4\] " "Info (13350): Duplicate register \"ADDRESS\[4\]\" merged to single register \"DATA\[4\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ADDRESS\[5\] DATA\[5\] " "Info (13350): Duplicate register \"ADDRESS\[5\]\" merged to single register \"DATA\[5\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ADDRESS\[6\] DATA\[6\] " "Info (13350): Duplicate register \"ADDRESS\[6\]\" merged to single register \"DATA\[6\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ADDRESS\[7\] DATA\[7\] " "Info (13350): Duplicate register \"ADDRESS\[7\]\" merged to single register \"DATA\[7\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "data_buffer:b\|data~17 " "Warning: Inferred dual-clock RAM node \"data_buffer:b\|data~17\" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." {  } { { "BUFFER.vhd" "data~17" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/BUFFER.vhd" 18 -1 0 } }  } 0 0 "Inferred dual-clock RAM node \"%1!s!\" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." 0 0 "" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "data_buffer:b\|data~17 " "Info: Inferred altsyncram megafunction from the following design logic: \"data_buffer:b\|data~17\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Info: Parameter OPERATION_MODE set to DUAL_PORT" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Info: Parameter WIDTH_A set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 8 " "Info: Parameter WIDTHAD_A set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 256 " "Info: Parameter NUMWORDS_A set to 256" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Info: Parameter WIDTH_B set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 8 " "Info: Parameter WIDTHAD_B set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 256 " "Info: Parameter NUMWORDS_B set to 256" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter OUTDATA_REG_B set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Info: Parameter ADDRESS_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Info: Parameter OUTDATA_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK1 " "Info: Parameter ADDRESS_REG_B set to CLOCK1" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0}  } { { "BUFFER.vhd" "data~17" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/BUFFER.vhd" 18 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "data_buffer:b\|altsyncram:data_rtl_0 " "Info: Elaborated megafunction instantiation \"data_buffer:b\|altsyncram:data_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "data_buffer:b\|altsyncram:data_rtl_0 " "Info: Instantiated megafunction \"data_buffer:b\|altsyncram:data_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Info: Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Info: Parameter \"WIDTH_A\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 8 " "Info: Parameter \"WIDTHAD_A\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 256 " "Info: Parameter \"NUMWORDS_A\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Info: Parameter \"WIDTH_B\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 8 " "Info: Parameter \"WIDTHAD_B\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 256 " "Info: Parameter \"NUMWORDS_B\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Info: Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Info: Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK1 " "Info: Parameter \"ADDRESS_REG_B\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Info: Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3te1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3te1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3te1 " "Info: Found entity 1: altsyncram_3te1" {  } { { "db/altsyncram_3te1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_3te1.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6gi1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_6gi1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6gi1 " "Info: Found entity 1: altsyncram_6gi1" {  } { { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[1\] GND " "Warning (13410): Pin \"LEDR\[1\]\" is stuck at GND" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[2\] GND " "Warning (13410): Pin \"LEDR\[2\]\" is stuck at GND" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[3\] GND " "Warning (13410): Pin \"LEDR\[3\]\" is stuck at GND" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[4\] GND " "Warning (13410): Pin \"LEDR\[4\]\" is stuck at GND" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[5\] GND " "Warning (13410): Pin \"LEDR\[5\]\" is stuck at GND" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[6\] GND " "Warning (13410): Pin \"LEDR\[6\]\" is stuck at GND" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[7\] GND " "Warning (13410): Pin \"LEDR\[7\]\" is stuck at GND" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[8\] GND " "Warning (13410): Pin \"LEDR\[8\]\" is stuck at GND" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[9\] GND " "Warning (13410): Pin \"LEDR\[9\]\" is stuck at GND" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "6 " "Warning: Design contains 6 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "Warning (15610): No output dependent on input pin \"SW\[8\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 9 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning (15610): No output dependent on input pin \"SW\[9\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 9 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "Warning (15610): No output dependent on input pin \"KEY\[0\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 12 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning (15610): No output dependent on input pin \"KEY\[1\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 12 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "Warning (15610): No output dependent on input pin \"KEY\[2\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 12 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "Warning (15610): No output dependent on input pin \"KEY\[3\]\"" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 12 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "62 " "Info: Implemented 62 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 40 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 40 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "196 " "Info: Peak virtual memory: 196 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 20:59:51 2008 " "Info: Processing ended: Mon Oct 27 20:59:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}