prev_cmp_databuffer.map.qmsg

buffer for in/out data.

{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[1\] DATABUFFER.vhd(10) " "Warning (10034): Output port \"LEDR\[1\]\" at DATABUFFER.vhd(10) has no driver" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClockGen ClockGen:SI " "Info: Elaborating entity \"ClockGen\" for hierarchy \"ClockGen:SI\"" {  } { { "DATABUFFER.vhd" "SI" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 65 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "count100K ClockGen.vhd(18) " "Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(18): used explicit default value for signal \"count100K\" because signal was never assigned a value" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 18 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "count10K ClockGen.vhd(19) " "Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(19): used explicit default value for signal \"count10K\" because signal was never assigned a value" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 19 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "count1K ClockGen.vhd(20) " "Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(20): used explicit default value for signal \"count1K\" because signal was never assigned a value" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 20 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "count100 ClockGen.vhd(21) " "Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(21): used explicit default value for signal \"count100\" because signal was never assigned a value" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 21 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "count10 ClockGen.vhd(22) " "Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(22): used explicit default value for signal \"count10\" because signal was never assigned a value" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 22 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "count1 ClockGen.vhd(23) " "Warning (10540): VHDL Signal Declaration warning at ClockGen.vhd(23): used explicit default value for signal \"count1\" because signal was never assigned a value" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 23 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count1M ClockGen.vhd(34) " "Warning (10492): VHDL Process Statement warning at ClockGen.vhd(34): signal \"count1M\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count100K ClockGen.vhd(51) " "Warning (10492): VHDL Process Statement warning at ClockGen.vhd(51): signal \"count100K\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 51 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count10K ClockGen.vhd(67) " "Warning (10492): VHDL Process Statement warning at ClockGen.vhd(67): signal \"count10K\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 67 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count1K ClockGen.vhd(83) " "Warning (10492): VHDL Process Statement warning at ClockGen.vhd(83): signal \"count1K\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 83 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count100 ClockGen.vhd(99) " "Warning (10492): VHDL Process Statement warning at ClockGen.vhd(99): signal \"count100\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 99 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count10 ClockGen.vhd(115) " "Warning (10492): VHDL Process Statement warning at ClockGen.vhd(115): signal \"count10\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 115 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count1 ClockGen.vhd(131) " "Warning (10492): VHDL Process Statement warning at ClockGen.vhd(131): signal \"count1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 131 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}