prev_cmp_databuffer.map.qmsg

buffer for in/out data.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 27 20:59:49 2008 " "Info: Processing started: Mon Oct 27 20:59:49 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DATABUFFER -c DATABUFFER " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DATABUFFER -c DATABUFFER" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../ClockGen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../ClockGen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ClockGen-behav " "Info: Found design unit 1: ClockGen-behav" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ClockGen " "Info: Found entity 1: ClockGen" {  } { { "../ClockGen.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/ClockGen.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BUFFER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file BUFFER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_buffer-RTL " "Info: Found design unit 1: data_buffer-RTL" {  } { { "BUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/BUFFER.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 data_buffer " "Info: Found entity 1: data_buffer" {  } { { "BUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/BUFFER.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DATABUFFER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DATABUFFER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DATABUFFER-struct " "Info: Found design unit 1: DATABUFFER-struct" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DATABUFFER " "Info: Found entity 1: DATABUFFER" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DATABUFFER " "Info: Elaborating entity \"DATABUFFER\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[9\] DATABUFFER.vhd(10) " "Warning (10034): Output port \"LEDR\[9\]\" at DATABUFFER.vhd(10) has no driver" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[8\] DATABUFFER.vhd(10) " "Warning (10034): Output port \"LEDR\[8\]\" at DATABUFFER.vhd(10) has no driver" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[7\] DATABUFFER.vhd(10) " "Warning (10034): Output port \"LEDR\[7\]\" at DATABUFFER.vhd(10) has no driver" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[6\] DATABUFFER.vhd(10) " "Warning (10034): Output port \"LEDR\[6\]\" at DATABUFFER.vhd(10) has no driver" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[5\] DATABUFFER.vhd(10) " "Warning (10034): Output port \"LEDR\[5\]\" at DATABUFFER.vhd(10) has no driver" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[4\] DATABUFFER.vhd(10) " "Warning (10034): Output port \"LEDR\[4\]\" at DATABUFFER.vhd(10) has no driver" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[3\] DATABUFFER.vhd(10) " "Warning (10034): Output port \"LEDR\[3\]\" at DATABUFFER.vhd(10) has no driver" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[2\] DATABUFFER.vhd(10) " "Warning (10034): Output port \"LEDR\[2\]\" at DATABUFFER.vhd(10) has no driver" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}