prev_cmp_databuffer.tan.qmsg

buffer for in/out data.

{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 LEDG\[5\] data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg0 11.400 ns memory " "Info: tco from clock \"CLOCK_50\" to destination pin \"LEDG\[5\]\" through memory \"data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg0\" is 11.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.933 ns + Longest memory " "Info: + Longest clock path from clock \"CLOCK_50\" to source memory is 2.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.747 ns) 2.933 ns data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg0 3 MEM M4K_X41_Y9 8 " "Info: 3: + IC(0.922 ns) + CELL(0.747 ns) = 2.933 ns; Loc. = M4K_X41_Y9; Fanout = 8; MEM Node = 'data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.669 ns" { CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.773 ns ( 60.45 % ) " "Info: Total cell delay = 1.773 ns ( 60.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.160 ns ( 39.55 % ) " "Info: Total interconnect delay = 1.160 ns ( 39.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.933 ns" { CLOCK_50 CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.933 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.238ns 0.922ns } { 0.000ns 1.026ns 0.000ns 0.747ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.234 ns + " "Info: + Micro clock to output delay of source is 0.234 ns" {  } { { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.233 ns + Longest memory pin " "Info: + Longest memory to pin delay is 8.233 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg0 1 MEM M4K_X41_Y9 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X41_Y9; Fanout = 8; MEM Node = 'data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.377 ns) 3.377 ns data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|q_a\[5\] 2 MEM M4K_X41_Y9 1 " "Info: 2: + IC(0.000 ns) + CELL(3.377 ns) = 3.377 ns; Loc. = M4K_X41_Y9; Fanout = 1; MEM Node = 'data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|q_a\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.377 ns" { data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|q_a[5] } "NODE_NAME" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.996 ns) + CELL(2.860 ns) 8.233 ns LEDG\[5\] 3 PIN PIN_W21 0 " "Info: 3: + IC(1.996 ns) + CELL(2.860 ns) = 8.233 ns; Loc. = PIN_W21; Fanout = 0; PIN Node = 'LEDG\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.856 ns" { data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|q_a[5] LEDG[5] } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.237 ns ( 75.76 % ) " "Info: Total cell delay = 6.237 ns ( 75.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.996 ns ( 24.24 % ) " "Info: Total interconnect delay = 1.996 ns ( 24.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|q_a[5] LEDG[5] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|q_a[5] {} LEDG[5] {} } { 0.000ns 0.000ns 1.996ns } { 0.000ns 3.377ns 2.860ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.933 ns" { CLOCK_50 CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.933 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.238ns 0.922ns } { 0.000ns 1.026ns 0.000ns 0.747ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|q_a[5] LEDG[5] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg0 {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|q_a[5] {} LEDG[5] {} } { 0.000ns 0.000ns 1.996ns } { 0.000ns 3.377ns 2.860ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CLOCK_50 LEDR\[0\] 6.016 ns Longest " "Info: Longest tpd from source pin \"CLOCK_50\" to destination pin \"LEDR\[0\]\" is 6.016 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.150 ns) + CELL(2.840 ns) 6.016 ns LEDR\[0\] 2 PIN PIN_R20 0 " "Info: 2: + IC(2.150 ns) + CELL(2.840 ns) = 6.016 ns; Loc. = PIN_R20; Fanout = 0; PIN Node = 'LEDR\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.990 ns" { CLOCK_50 LEDR[0] } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.866 ns ( 64.26 % ) " "Info: Total cell delay = 3.866 ns ( 64.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.150 ns ( 35.74 % ) " "Info: Total interconnect delay = 2.150 ns ( 35.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.016 ns" { CLOCK_50 LEDR[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.016 ns" { CLOCK_50 {} CLOCK_50~combout {} LEDR[0] {} } { 0.000ns 0.000ns 2.150ns } { 0.000ns 1.026ns 2.840ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg2 SW\[2\] CLOCK_50 0.353 ns memory " "Info: th for memory \"data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg2\" (data pin = \"SW\[2\]\", clock pin = \"CLOCK_50\") is 0.353 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.933 ns + Longest memory " "Info: + Longest clock path from clock \"CLOCK_50\" to destination memory is 2.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.747 ns) 2.933 ns data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg2 3 MEM M4K_X41_Y9 8 " "Info: 3: + IC(0.922 ns) + CELL(0.747 ns) = 2.933 ns; Loc. = M4K_X41_Y9; Fanout = 8; MEM Node = 'data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg2'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.669 ns" { CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 } "NODE_NAME" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.773 ns ( 60.45 % ) " "Info: Total cell delay = 1.773 ns ( 60.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.160 ns ( 39.55 % ) " "Info: Total interconnect delay = 1.160 ns ( 39.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.933 ns" { CLOCK_50 CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.933 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 {} } { 0.000ns 0.000ns 0.238ns 0.922ns } { 0.000ns 1.026ns 0.000ns 0.747ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.250 ns + " "Info: + Micro hold delay of destination is 0.250 ns" {  } { { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.830 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns SW\[2\] 1 PIN PIN_M22 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_M22; Fanout = 1; PIN Node = 'SW\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.635 ns) + CELL(0.159 ns) 2.830 ns data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg2 2 MEM M4K_X41_Y9 8 " "Info: 2: + IC(1.635 ns) + CELL(0.159 ns) = 2.830 ns; Loc. = M4K_X41_Y9; Fanout = 8; MEM Node = 'data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg2'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.794 ns" { SW[2] data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 } "NODE_NAME" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.195 ns ( 42.23 % ) " "Info: Total cell delay = 1.195 ns ( 42.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.635 ns ( 57.77 % ) " "Info: Total interconnect delay = 1.635 ns ( 57.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { SW[2] data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { SW[2] {} SW[2]~combout {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 {} } { 0.000ns 0.000ns 1.635ns } { 0.000ns 1.036ns 0.159ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.933 ns" { CLOCK_50 CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.933 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 {} } { 0.000ns 0.000ns 0.238ns 0.922ns } { 0.000ns 1.026ns 0.000ns 0.747ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { SW[2] data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { SW[2] {} SW[2]~combout {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg2 {} } { 0.000ns 0.000ns 1.635ns } { 0.000ns 1.036ns 0.159ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}