prev_cmp_databuffer.tan.qmsg

buffer for in/out data.

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLOCK_50 register memory COUNT\[0\] data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~portb_address_reg0 195.01 MHz Internal " "Info: Clock \"CLOCK_50\" Internal fmax is restricted to 195.01 MHz between source register \"COUNT\[0\]\" and destination memory \"data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~portb_address_reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.564 ns 2.564 ns 5.128 ns " "Info: fmax restricted to Clock High delay (2.564 ns) plus Clock Low delay (2.564 ns) : restricted to 5.128 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.657 ns + Longest register memory " "Info: + Longest register to memory delay is 1.657 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNT\[0\] 1 REG LCFF_X43_Y9_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y9_N1; Fanout = 5; REG Node = 'COUNT\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { COUNT[0] } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(0.177 ns) 0.544 ns COUNT\[0\]~_wirecell 2 COMB LCCOMB_X43_Y9_N22 2 " "Info: 2: + IC(0.367 ns) + CELL(0.177 ns) = 0.544 ns; Loc. = LCCOMB_X43_Y9_N22; Fanout = 2; COMB Node = 'COUNT\[0\]~_wirecell'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.544 ns" { COUNT[0] COUNT[0]~_wirecell } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.954 ns) + CELL(0.159 ns) 1.657 ns data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~portb_address_reg0 3 MEM M4K_X41_Y9 0 " "Info: 3: + IC(0.954 ns) + CELL(0.159 ns) = 1.657 ns; Loc. = M4K_X41_Y9; Fanout = 0; MEM Node = 'data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~portb_address_reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.113 ns" { COUNT[0]~_wirecell data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.336 ns ( 20.28 % ) " "Info: Total cell delay = 0.336 ns ( 20.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.321 ns ( 79.72 % ) " "Info: Total interconnect delay = 1.321 ns ( 79.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { COUNT[0] COUNT[0]~_wirecell data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.657 ns" { COUNT[0] {} COUNT[0]~_wirecell {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 {} } { 0.000ns 0.367ns 0.954ns } { 0.000ns 0.177ns 0.159ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.113 ns - Smallest " "Info: - Smallest clock skew is 0.113 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.969 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination memory is 2.969 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.783 ns) 2.969 ns data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~portb_address_reg0 3 MEM M4K_X41_Y9 0 " "Info: 3: + IC(0.922 ns) + CELL(0.783 ns) = 2.969 ns; Loc. = M4K_X41_Y9; Fanout = 0; MEM Node = 'data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~portb_address_reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.705 ns" { CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.809 ns ( 60.93 % ) " "Info: Total cell delay = 1.809 ns ( 60.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.160 ns ( 39.07 % ) " "Info: Total interconnect delay = 1.160 ns ( 39.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.969 ns" { CLOCK_50 CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.969 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.238ns 0.922ns } { 0.000ns 1.026ns 0.000ns 0.783ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.856 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.602 ns) 2.856 ns COUNT\[0\] 3 REG LCFF_X43_Y9_N1 5 " "Info: 3: + IC(0.990 ns) + CELL(0.602 ns) = 2.856 ns; Loc. = LCFF_X43_Y9_N1; Fanout = 5; REG Node = 'COUNT\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { CLOCK_50~clkctrl COUNT[0] } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.00 % ) " "Info: Total cell delay = 1.628 ns ( 57.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.228 ns ( 43.00 % ) " "Info: Total interconnect delay = 1.228 ns ( 43.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl COUNT[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} COUNT[0] {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.969 ns" { CLOCK_50 CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.969 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.238ns 0.922ns } { 0.000ns 1.026ns 0.000ns 0.783ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl COUNT[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} COUNT[0] {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.040 ns + " "Info: + Micro setup delay of destination is 0.040 ns" {  } { { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 51 -1 0 } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { COUNT[0] COUNT[0]~_wirecell data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.657 ns" { COUNT[0] {} COUNT[0]~_wirecell {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 {} } { 0.000ns 0.367ns 0.954ns } { 0.000ns 0.177ns 0.159ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.969 ns" { CLOCK_50 CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.969 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.238ns 0.922ns } { 0.000ns 1.026ns 0.000ns 0.783ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl COUNT[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} COUNT[0] {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~portb_address_reg0 {} } {  } {  } "" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg5 SW\[5\] CLOCK_50 0.585 ns memory " "Info: tsu for memory \"data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg5\" (data pin = \"SW\[5\]\", clock pin = \"CLOCK_50\") is 0.585 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.478 ns + Longest pin memory " "Info: + Longest pin to memory delay is 3.478 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns SW\[5\] 1 PIN PIN_U12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_U12; Fanout = 1; PIN Node = 'SW\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[5] } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.313 ns) + CELL(0.159 ns) 3.478 ns data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg5 2 MEM M4K_X41_Y9 8 " "Info: 2: + IC(2.313 ns) + CELL(0.159 ns) = 3.478 ns; Loc. = M4K_X41_Y9; Fanout = 8; MEM Node = 'data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { SW[5] data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 } "NODE_NAME" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.165 ns ( 33.50 % ) " "Info: Total cell delay = 1.165 ns ( 33.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.313 ns ( 66.50 % ) " "Info: Total interconnect delay = 2.313 ns ( 66.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.478 ns" { SW[5] data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.478 ns" { SW[5] {} SW[5]~combout {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 {} } { 0.000ns 0.000ns 2.313ns } { 0.000ns 1.006ns 0.159ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.040 ns + " "Info: + Micro setup delay of destination is 0.040 ns" {  } { { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.933 ns - Shortest memory " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination memory is 2.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DATABUFFER.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/DATABUFFER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.747 ns) 2.933 ns data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg5 3 MEM M4K_X41_Y9 8 " "Info: 3: + IC(0.922 ns) + CELL(0.747 ns) = 2.933 ns; Loc. = M4K_X41_Y9; Fanout = 8; MEM Node = 'data_buffer:b\|altsyncram:data_rtl_0\|altsyncram_3te1:auto_generated\|altsyncram_6gi1:altsyncram1\|ram_block2a0~porta_address_reg5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.669 ns" { CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 } "NODE_NAME" } } { "db/altsyncram_6gi1.tdf" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/BUFFER/db/altsyncram_6gi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.773 ns ( 60.45 % ) " "Info: Total cell delay = 1.773 ns ( 60.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.160 ns ( 39.55 % ) " "Info: Total interconnect delay = 1.160 ns ( 39.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.933 ns" { CLOCK_50 CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.933 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 {} } { 0.000ns 0.000ns 0.238ns 0.922ns } { 0.000ns 1.026ns 0.000ns 0.747ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.478 ns" { SW[5] data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.478 ns" { SW[5] {} SW[5]~combout {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 {} } { 0.000ns 0.000ns 2.313ns } { 0.000ns 1.006ns 0.159ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.933 ns" { CLOCK_50 CLOCK_50~clkctrl data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.933 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} data_buffer:b|altsyncram:data_rtl_0|altsyncram_3te1:auto_generated|altsyncram_6gi1:altsyncram1|ram_block2a0~porta_address_reg5 {} } { 0.000ns 0.000ns 0.238ns 0.922ns } { 0.000ns 1.026ns 0.000ns 0.747ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}