buffer.vhd

buffer for in/out data.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity data_buffer is
port(
	wen: in std_logic;
	oen: in std_logic;
	raddress: in std_logic_vector(7 downto 0);
	waddress: in std_logic_vector(7 downto 0);
	datain: in std_logic_vector(7 downto 0);
	dataout: out std_logic_vector(7 downto 0)
	);
end data_buffer;

architecture RTL of data_buffer is
type buff is array (0 to 255) of std_logic_vector(7 downto 0);
signal data: buff;
signal dout: std_logic_vector(7 downto 0);
begin
	bread: process(oen)
	begin
		if (oen'event and oen = '1') then
			dout <= data(conv_integer(raddress));
		end if;
	end process;
	
	bwrite: process(wen)
	begin
		if (wen'event and wen = '1') then
			data(conv_integer(Waddress)) <= datain;
		end if;
	end process;
	dataout <= dout;
end RTL;