ring_counter.v

来自「利用电话远程系统」· Verilog 代码 · 共 31 行

`timescale 1ns/10ps

module ring_counter(ring_c,clr,enable,rst);
    input ring_c;
    input clr;
    input rst;
    output enable;
    
    reg enable;
    reg [2:0] ring_counter;
    
always@(negedge ring_c or negedge clr or negedge rst)
begin
    if(rst==0)
    begin
        ring_counter  <= 3'b000;
        enable        <= 1'b0;
    end
    else if(clr==1'b0)
    begin
        ring_counter  <= 3'b000;
        enable        <= 1'b0;
    end
    else if (ring_counter==3'b101)
        enable  <=  1'b1;
    else
        ring_counter  <= ring_counter+1;
end
endmodule