dtmf_h_check.v

来自「利用电话远程系统」· Verilog 代码 · 共 60 行

`timescale 1ns/10ps

module dtmf_h_check(dtmf_h,dtmf_high,dtmf_low,clk,rst,dtmf_clr);
input dtmf_h;
input dtmf_clr;
input clk,rst;
output dtmf_high;
output dtmf_low;
reg dtmf_high;
reg dtmf_low;

reg [9:0] data_high;
reg [9:0] data_low;

always@(posedge clk or negedge rst or negedge dtmf_clr)
begin
    if(rst==0)
    begin
        data_high   <= 10'b0000000000;
        dtmf_high   <= 1'b0;
    end
    else if(dtmf_clr==0)
    begin
        data_high   <= 10'b0000000000;
        dtmf_high   <= 1'b0;
    end
    else 
    begin
       if(data_high==10'b11111_11111)
           dtmf_high  <= 1'b1;
       else
           data_high <= {data_high[8:0],dtmf_h};
    end
end

always@(posedge clk or negedge rst)
begin
    if(rst==0)
    begin
        data_low    <= 10'b1010101010;
        dtmf_low    <= 1'b0;
    end
    else
    begin
        data_low  <= {data_low[8:0],dtmf_h};
        if(data_low==10'b0000000000)
            dtmf_low  <= 1'b1;
        else if(data_low==10'b1111111111)
           dtmf_low  <= 1'b0;
    end
end

endmodule