de2_top.tan.rpt

DE2 S O P C 用硬件语言 描述地 开发板上测试 CLM模块 实现视频传输

programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------------------+------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                                    ; From                                                  ; To                                                         ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------------------+------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 5.417 ns                                       ; TD_DATA[5]                                            ; TV_SET:NTSC|decode_656:decoMAIN|VS                         ; --                           ; CLOCK_27                     ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 15.314 ns                                      ; I2C_AV_Config:u3|I2C_Controller:u0|SD_COUNTER[0]~reg0 ; I2C_SCLK                                                   ; CLOCK_27                     ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 5.331 ns                                       ; CLOCK_27                                              ; GPIO_0[29]                                                 ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 1.810 ns                                       ; altera_internal_jtag                                  ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 92.25 MHz ( period = 10.840 ns )               ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5]    ; sld_hub:sld_hub_inst|hub_tdo                               ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLOCK_27'                     ; N/A   ; None          ; 136.46 MHz ( period = 7.328 ns )               ; TV_SET:NTSC|decode_656:decoMAIN|R1[3]                 ; TV_SET:NTSC|decode_656:decoMAIN|START                      ; CLOCK_27                     ; CLOCK_27                     ; 0            ;
; Clock Setup: 'TD_VS'                        ; N/A   ; None          ; 360.49 MHz ( period = 2.774 ns )               ; TV_SET:NTSC|Fcnt[7]                                   ; TV_SET:NTSC|Fcnt[7]                                        ; TD_VS                        ; TD_VS                        ; 0            ;
; Clock Setup: 'CLOCK_50'                     ; N/A   ; None          ; 386.85 MHz ( period = 2.585 ns )               ; TV_SET:NTSC|syst[1]                                   ; TV_SET:NTSC|syst[5]                                        ; CLOCK_50                     ; CLOCK_50                     ; 0            ;
; Clock Setup: 'TD_HS'                        ; N/A   ; None          ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; TV_SET:NTSC|L_COUNTER[0]                              ; TV_SET:NTSC|L_COUNTER[10]                                  ; TD_HS                        ; TD_HS                        ; 0            ;
; Total number of failed paths                ;       ;               ;                                                ;                                                       ;                                                            ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------------------+------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;