de2_top.map.rpt

DE2 S O P C 用硬件语言 描述地 开发板上测试 CLM模块 实现视频传输

Analysis & Synthesis report for DE2_TOP
Fri May 12 10:39:02 2006
Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |DE2_TOP|I2C_AV_Config:u3|mSetup_ST
  9. State Machine - |DE2_TOP|I2S_LCM_Config:u1|mSetup_ST
 10. User-Specified and Inferred Latches
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for sld_signaltap:auto_signaltap_0
 15. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_jrb2:auto_generated
 16. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_jrb2:auto_generated|altsyncram_9cc1:altsyncram1
 17. Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr
 18. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 19. Parameter Settings for User Entity Instance: I2S_LCM_Config:u1
 20. Parameter Settings for User Entity Instance: I2S_LCM_Config:u1|I2S_Controller:u0
 21. Parameter Settings for User Entity Instance: I2C_AV_Config:u3
 22. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 23. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 24. SignalTap II Logic Analyzer Settings
 25. Analysis & Synthesis Equations
 26. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri May 12 10:39:01 2006         ;
; Quartus II Version                 ; 5.1 Build 216 03/06/2006 SP 2 SJ Full Version ;
; Revision Name                      ; DE2_TOP                                       ;
; Top-level Entity Name              ; DE2_TOP                                       ;