⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 alu_4bit.twr

📁 this program performs the functonality of 4 bit alu
💻 TWR
字号:
--------------------------------------------------------------------------------
Release 6.3i Trace G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

E:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml alu_4bit alu_4bit.ncd -o
alu_4bit.twr alu_4bit.pcf


Design file:              alu_4bit.ncd
Physical constraint file: alu_4bit.pcf
Device,speed:             xc3s50,-5 (ADVANCED 1.32 2004-06-25)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk1
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
ce          |    3.935(R)|   -1.843(R)|clk1_BUFGP        |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock m
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
ain<0>      |    3.870(R)|    3.024(R)|m_BUFGP           |   0.000|
            |   -0.494(F)|    2.506(F)|m_BUFGP           |   0.000|
ain<1>      |    2.850(R)|    3.046(R)|m_BUFGP           |   0.000|
            |   -0.601(F)|    2.592(F)|m_BUFGP           |   0.000|
ain<2>      |    1.252(R)|    3.203(R)|m_BUFGP           |   0.000|
            |   -0.334(F)|    2.378(F)|m_BUFGP           |   0.000|
ain<3>      |    0.382(R)|    3.164(R)|m_BUFGP           |   0.000|
            |   -0.285(F)|    2.340(F)|m_BUFGP           |   0.000|
bin<0>      |    3.654(R)|    2.665(R)|m_BUFGP           |   0.000|
            |   -0.647(F)|    2.629(F)|m_BUFGP           |   0.000|
bin<1>      |    3.074(R)|    2.492(R)|m_BUFGP           |   0.000|
            |   -0.013(F)|    2.122(F)|m_BUFGP           |   0.000|
bin<2>      |    2.236(R)|    2.524(R)|m_BUFGP           |   0.000|
            |    0.132(F)|    2.006(F)|m_BUFGP           |   0.000|
bin<3>      |    2.150(R)|    1.813(R)|m_BUFGP           |   0.000|
            |    0.485(F)|    1.724(F)|m_BUFGP           |   0.000|
cin         |    2.087(R)|    2.245(R)|m_BUFGP           |   0.000|
sel         |    4.437(R)|    2.457(R)|m_BUFGP           |   0.000|
            |    0.828(F)|    2.304(F)|m_BUFGP           |   0.000|
------------+------------+------------+------------------+--------+

Clock m to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
sout<0>     |    9.340(F)|m_BUFGP           |   0.000|
sout<1>     |    9.340(F)|m_BUFGP           |   0.000|
sout<2>     |    9.340(F)|m_BUFGP           |   0.000|
sout<3>     |    9.340(F)|m_BUFGP           |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk1
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk1           |    4.466|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock m
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
m              |    3.288|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
ain<0>         |cout           |   10.888|
ain<1>         |cout           |    9.748|
ain<2>         |cout           |    8.717|
ain<3>         |cout           |    7.779|
bin<0>         |cout           |   11.095|
bin<1>         |cout           |   10.364|
bin<2>         |cout           |    9.851|
bin<3>         |cout           |    8.733|
cin            |cout           |   11.141|
---------------+---------------+---------+

Analysis completed Tue Feb 14 12:44:49 2006
--------------------------------------------------------------------------------

Peak Memory Usage: 46 MB

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -