alu_4bit.par

this program performs the functonality of 4 bit alu

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

P4::  Tue Feb 14 12:44:45 2006


E:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 alu_4bit_map.ncd
alu_4bit.ncd alu_4bit.pcf 


Constraints file: alu_4bit.pcf

Loading device database for application Par from file "alu_4bit_map.ncd".
   "alu_4bit" is an NCD, version 2.38, device xc3s50, package pq208, speed -5
Loading device for application Par from file '3s50.nph' in environment
E:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-25.


Resolved that IOB <ain<0>> must be placed at site P43.
Resolved that IOB <ain<1>> must be placed at site P40.
Resolved that IOB <ain<2>> must be placed at site P37.
Resolved that IOB <ain<3>> must be placed at site P35.
Resolved that IOB <m> must be placed at site P27.
Resolved that IOB <cin> must be placed at site P29.
Resolved that IOB <bin<0>> must be placed at site P58.
Resolved that IOB <bin<1>> must be placed at site P52.
Resolved that IOB <bin<2>> must be placed at site P48.
Resolved that IOB <bin<3>> must be placed at site P45.
Resolved that IOB <oen1> must be placed at site P2.
Resolved that IOB <oen2> must be placed at site P3.
Resolved that IOB <oen3> must be placed at site P7.
Resolved that IOB <oen4> must be placed at site P9.
Resolved that IOB <sel> must be placed at site P62.
Resolved that IOB <cout> must be placed at site P36.
Resolved that IOB <sout<0>> must be placed at site P34.
Resolved that IOB <clk1> must be placed at site P79.
Resolved that IOB <sout<1>> must be placed at site P28.
Resolved that IOB <sout<2>> must be placed at site P26.
Resolved that IOB <sout<3>> must be placed at site P20.
Resolved that IOB <dis_out<0>> must be placed at site P10.
Resolved that IOB <dis_out<1>> must be placed at site P11.
Resolved that IOB <dis_out<2>> must be placed at site P12.
Resolved that IOB <dis_out<3>> must be placed at site P13.
Resolved that IOB <dis_out<4>> must be placed at site P15.
Resolved that IOB <dis_out<5>> must be placed at site P16.
Resolved that IOB <ce> must be placed at site P21.
Resolved that IOB <dis_out<6>> must be placed at site P18.
Resolved that IOB <dis_out<7>> must be placed at site P19.


Device utilization summary:

   Number of External IOBs            30 out of 124    24%
      Number of LOCed External IOBs   30 out of 30    100%

   Number of Slices                   36 out of 768     4%

   Number of BUFGMUXs                  2 out of 8      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98974b) REAL time: 0 secs 

......
.........
Phase 3.8
.
Phase 3.8 (Checksum:98e620) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs 

Writing design to file alu_4bit.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 269 unrouted;       REAL time: 2 secs 

Phase 2: 234 unrouted;       REAL time: 2 secs 

Phase 3: 85 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|           m_BUFGP       |  BUFGMUX7| No   |   11 |  0.035     |  0.903      |
+-------------------------+----------+------+------+------------+-------------+
|        clk1_BUFGP       |  BUFGMUX0| No   |    4 |  0.000     |  0.868      |
+-------------------------+----------+------+------+------------+-------------+
|      u4_u1_dout_1       |   Local  |      |   33 |  0.017     |  1.685      |
+-------------------------+----------+------+------+------------+-------------+
|           u1_temp       |   Local  |      |    5 |  0.000     |  1.653      |
+-------------------------+----------+------+------+------------+-------------+
|           u2_temp       |   Local  |      |    3 |  0.000     |  1.623      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 123


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.910
   The MAXIMUM PIN DELAY IS:                               2.403
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.595

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         175          91           3           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file alu_4bit.ncd.


PAR done.