alu_4bit.syr

this program performs the functonality of 4 bit alu

# FlipFlops/Latches                : 38
#      FD                          : 2
#      FDC                         : 10
#      FDE                         : 2
#      LD                          : 4
#      LD_1                        : 1
#      LDCP_1                      : 8
#      LDE_1                       : 11
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 28
#      IBUF                        : 11
#      OBUF                        : 17
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-5 

 Number of Slices:                      38  out of    768     4%  
 Number of Slice Flip Flops:            38  out of   1536     2%  
 Number of 4 input LUTs:                67  out of   1536     4%  
 Number of bonded IOBs:                 28  out of    124    22%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
m                                  | BUFGP                  | 16    |
clk1                               | BUFGP                  | 6     |
u1_temp:Q                          | NONE                   | 6     |
u4_u1_dout_1:Q                     | NONE                   | 8     |
u2_temp:Q                          | NONE                   | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 2.802ns (Maximum Frequency: 356.888MHz)
   Minimum input arrival time before clock: 6.262ns
   Maximum output required time after clock: 6.275ns
   Maximum combinational path delay: 9.678ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk1'
Delay:               2.802ns (Levels of Logic = 2)
  Source:            u1_cnt_0 (FF)
  Destination:       u1_cnt_3 (FF)
  Source Clock:      clk1 rising
  Destination Clock: clk1 rising

  Data Path: u1_cnt_0 to u1_cnt_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.626   0.577  u1_cnt_0 (u1_cnt_0)
     LUT2_D:I1->O          2   0.479   0.465  u1_Madd__n0005__n00001 (u1_Madd__n0005__n0005<0>)
     LUT4_L:I3->LO         1   0.479   0.000  u1__n0001<4>1 (u1__n0001<4>)
     FDC:D                     0.176          u1_cnt_4
    ----------------------------------------
    Total                      2.802ns (1.760ns logic, 1.042ns route)
                                       (62.8% logic, 37.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_temp:Q'
Delay:               2.802ns (Levels of Logic = 2)
  Source:            u2_cnt_0 (FF)
  Destination:       u2_cnt_2 (FF)
  Source Clock:      u1_temp:Q rising
  Destination Clock: u1_temp:Q rising

  Data Path: u2_cnt_0 to u2_cnt_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.626   0.577  u2_cnt_0 (u2_cnt_0)
     LUT2_D:I1->O          2   0.479   0.465  u2_Madd__n0005__n00001 (u2_Madd__n0005__n0005<0>)
     LUT4_L:I3->LO         1   0.479   0.000  u2__n0001<4>1 (u2__n0001<4>)
     FDC:D                     0.176          u2_cnt_4
    ----------------------------------------
    Total                      2.802ns (1.760ns logic, 1.042ns route)
                                       (62.8% logic, 37.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'm'
Delay:               2.014ns (Levels of Logic = 1)
  Source:            dtemp_0 (LATCH)
  Destination:       dtemp_0 (LATCH)
  Source Clock:      m rising
  Destination Clock: m rising

  Data Path: dtemp_0 to dtemp_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             8   0.551   0.747  dtemp_0 (dtemp_0)
     MUXF5:S->O            1   0.540   0.000  Mmux__n0025_Result<0> (_n0025<0>)
     LD_1:D                    0.176          dtemp_0
    ----------------------------------------
    Total                      2.014ns (1.267ns logic, 0.747ns route)
                                       (62.9% logic, 37.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u2_temp:Q'
Delay:               1.746ns (Levels of Logic = 1)
  Source:            u4_u1_dout (FF)
  Destination:       u4_u1_dout (FF)
  Source Clock:      u2_temp:Q rising
  Destination Clock: u2_temp:Q rising

  Data Path: u4_u1_dout to u4_u1_dout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.626   0.465  u4_u1_dout (u4_u1_dout)
     LUT1:I0->O            1   0.479   0.000  u4_XLXI_7_o1_1 (N3178)
     FD:D                      0.176          u4_u1_dout_1
    ----------------------------------------
    Total                      1.746ns (1.281ns logic, 0.465ns route)
                                       (73.4% logic, 26.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'm'
Offset:              6.262ns (Levels of Logic = 6)
  Source:            sel (PAD)
  Destination:       dtemp_3 (LATCH)
  Destination Clock: m rising

  Data Path: sel to dtemp_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            13   1.679   0.895  sel_IBUF (sel_IBUF)
     LUT3:I2->O            2   0.479   0.465  Madd__n0028__n00001 (Madd__n0028__n0011<0>)
     LUT4:I2->O            3   0.479   0.577  Madd__n0028__n00011 (Madd__n0028__n0013<0>)
     LUT4:I3->O            1   0.479   0.000  Madd__n0028_Mxor_Result<3>_Xo<0>1_G (N3182)
     MUXF5:I1->O           1   0.314   0.240  Madd__n0028_Mxor_Result<3>_Xo<0>1 (Madd__n0028_Mxor_Result<3>_Xo<0>)
     LUT2:I1->O            1   0.479   0.000  Mmux__n0025_Result<3>11 (N3166)
     LDE_1:D                   0.176          dtemp_3
    ----------------------------------------
    Total                      6.262ns (4.085ns logic, 2.177ns route)
                                       (65.2% logic, 34.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4_u1_dout_1:Q'
Offset:              6.093ns (Levels of Logic = 6)
  Source:            bin<0> (PAD)
  Destination:       dis_out_6 (LATCH)
  Destination Clock: u4_u1_dout_1:Q rising

  Data Path: bin<0> to dis_out_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   1.679   0.658  bin_0_IBUF (bin_0_IBUF)
     LUT3:I0->O            1   0.479   0.240  u5_u1_cout1 (u5_c1)
     LUT3:I1->O            1   0.479   0.240  u5_u2_cout1 (u5_c2)
     LUT3:I1->O            1   0.479   0.240  u5_u3_cout1 (u5_c3)
     LUT3:I1->O            2   0.479   0.465  u5_u4_cout1 (cout_OBUF)
     LUT3:I1->O            1   0.479   0.000  _n0024<6>1 (_n0024<6>)
     LDCP_1:D                  0.176          dis_out_6
    ----------------------------------------
    Total                      6.093ns (4.250ns logic, 1.843ns route)
                                       (69.8% logic, 30.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u1_temp:Q'
Offset:              3.647ns (Levels of Logic = 2)
  Source:            ce (PAD)
  Destination:       u2_temp (FF)
  Destination Clock: u1_temp:Q rising

  Data Path: ce to u2_temp
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   1.679   0.865  ce_IBUF (ce_IBUF)
     LUT3_L:I1->LO         1   0.479   0.100  u2__n00021 (u2__n0002)
     FDE:CE                    0.524          u2_temp
    ----------------------------------------
    Total                      3.647ns (2.682ns logic, 0.965ns route)
                                       (73.5% logic, 26.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1'
Offset:              3.647ns (Levels of Logic = 2)
  Source:            ce (PAD)
  Destination:       u1_temp (FF)
  Destination Clock: clk1 rising

  Data Path: ce to u1_temp
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   1.679   0.865  ce_IBUF (ce_IBUF)
     LUT3_L:I1->LO         1   0.479   0.100  u1__n00021 (u1__n0002)
     FDE:CE                    0.524          u1_temp
    ----------------------------------------
    Total                      3.647ns (2.682ns logic, 0.965ns route)
                                       (73.5% logic, 26.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u2_temp:Q'
Offset:              6.275ns (Levels of Logic = 2)
  Source:            u4_u1_dout (FF)
  Destination:       oen2 (PAD)
  Source Clock:      u2_temp:Q rising

  Data Path: u4_u1_dout to oen2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.626   0.465  u4_u1_dout (u4_u1_dout)
     LUT1:I0->O            2   0.479   0.465  u4_XLXI_7_o1 (oen2_OBUF)
     OBUF:I->O                 4.240          oen2_OBUF (oen2)
    ----------------------------------------
    Total                      6.275ns (5.345ns logic, 0.930ns route)
                                       (85.2% logic, 14.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u4_u1_dout_1:Q'
Offset:              5.031ns (Levels of Logic = 1)
  Source:            dis_out_7 (LATCH)
  Destination:       dis_out<7> (PAD)
  Source Clock:      u4_u1_dout_1:Q rising

  Data Path: dis_out_7 to dis_out<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCP_1:G->Q           1   0.551   0.240  dis_out_7 (dis_out_7)
     OBUF:I->O                 4.240          dis_out_7_OBUF (dis_out<7>)
    ----------------------------------------
    Total                      5.031ns (4.791ns logic, 0.240ns route)
                                       (95.2% logic, 4.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'm'
Offset:              5.031ns (Levels of Logic = 1)
  Source:            stemp_3 (LATCH)
  Destination:       sout<3> (PAD)
  Source Clock:      m falling

  Data Path: stemp_3 to sout<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.551   0.240  stemp_3 (stemp_3)
     OBUF:I->O                 4.240          sout_3_OBUF (sout<3>)
    ----------------------------------------
    Total                      5.031ns (4.791ns logic, 0.240ns route)
                                       (95.2% logic, 4.8% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               9.678ns (Levels of Logic = 6)
  Source:            bin<0> (PAD)
  Destination:       cout (PAD)

  Data Path: bin<0> to cout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   1.679   0.658  bin_0_IBUF (bin_0_IBUF)
     LUT3:I0->O            1   0.479   0.240  u5_u1_cout1 (u5_c1)
     LUT3:I1->O            1   0.479   0.240  u5_u2_cout1 (u5_c2)
     LUT3:I1->O            1   0.479   0.240  u5_u3_cout1 (u5_c3)
     LUT3:I1->O            2   0.479   0.465  u5_u4_cout1 (cout_OBUF)
     OBUF:I->O                 4.240          cout_OBUF (cout)
    ----------------------------------------
    Total                      9.678ns (7.835ns logic, 1.843ns route)
                                       (81.0% logic, 19.0% route)

=========================================================================
CPU : 12.55 / 14.22 s | Elapsed : 12.00 / 14.00 s
 
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Total memory usage is 66808 kilobytes