alu_4bit.syr

this program performs the functonality of 4 bit alu

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.86 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.86 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: alu_4bit.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : alu_4bit.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : alu_4bit
Output Format                      : NGC
Target Device                      : xc3s50-5-pq208

---- Source Options
Top Module Name                    : alu_4bit
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : alu_4bit.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fbitaddr.vhd in Library work.
Architecture behavioral of Entity fbitaddr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd in Library work.
Entity <alu_4bit> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <alu_4bit> (Architecture <behavioral>).
WARNING:Xst:819 - G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd line 91: The following signals are missing in the process sensitivity list:
   tempcout, tempdis.
WARNING:Xst:819 - G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd line 112: The following signals are missing in the process sensitivity list:
   ain, bin.
Entity <alu_4bit> analyzed. Unit <alu_4bit> generated.

Analyzing Entity <testcnt> (Architecture <behavioral>).
Entity <testcnt> analyzed. Unit <testcnt> generated.

Analyzing Entity <dflip> (Architecture <behavioral>).
Entity <dflip> analyzed. Unit <dflip> generated.

Analyzing Entity <dflipflop> (Architecture <behavioral>).
Entity <dflipflop> analyzed. Unit <dflipflop> generated.

Analyzing Entity <invtr> (Architecture <behavioral>).
Entity <invtr> analyzed. Unit <invtr> generated.

Analyzing Entity <buff> (Architecture <behavioral>).
Entity <buff> analyzed. Unit <buff> generated.

Analyzing Entity <fbitaddr> (Architecture <behavioral>).
Entity <fbitaddr> analyzed. Unit <fbitaddr> generated.

Analyzing Entity <fulladdr> (Architecture <behavioral>).
Entity <fulladdr> analyzed. Unit <fulladdr> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fulladdr>.
    Related source file is G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd.
Unit <fulladdr> synthesized.


Synthesizing Unit <buff>.
    Related source file is G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd.
Unit <buff> synthesized.


Synthesizing Unit <invtr>.
    Related source file is G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd.
Unit <invtr> synthesized.


Synthesizing Unit <dflipflop>.
    Related source file is G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd.
    Found 1-bit register for signal <dout>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <dflipflop> synthesized.


Synthesizing Unit <fbitaddr>.
    Related source file is G:/vijay_FPGA_LAB/4bit_alu/fbitaddr.vhd.
Unit <fbitaddr> synthesized.


Synthesizing Unit <dflip>.
    Related source file is G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd.
WARNING:Xst:1780 - Signal <temp2> is never used or assigned.
Unit <dflip> synthesized.


Synthesizing Unit <testcnt>.
    Related source file is G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd.
    Found 5-bit comparator less for signal <$n0004> created at line 25.
    Found 5-bit adder for signal <$n0005> created at line 26.
    Found 5-bit register for signal <cnt>.
    Found 1-bit register for signal <temp>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <testcnt> synthesized.


Synthesizing Unit <alu_4bit>.
    Related source file is G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd.
WARNING:Xst:646 - Signal <tempsout> is assigned but never used.
WARNING:Xst:737 - Found 8-bit latch for signal <dis_out>.
WARNING:Xst:737 - Found 4-bit latch for signal <dtemp>.
WARNING:Xst:737 - Found 8-bit latch for signal <tempdis>.
WARNING:Xst:737 - Found 4-bit latch for signal <stemp>.
    Found 16x8-bit ROM for signal <temp_out>.
    Found 4-bit adder for signal <$n0028> created at line 117.
    Found 17 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Adder/Subtracter(s).
	inferred  17 Multiplexer(s).
Unit <alu_4bit> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 3
 4-bit adder                       : 1
 5-bit adder                       : 2
# Registers                        : 6
 1-bit register                    : 4
 5-bit register                    : 2
# Latches                          : 4
 4-bit latch                       : 2
 8-bit latch                       : 2
# Comparators                      : 2
 5-bit comparator less             : 2
# Multiplexers                     : 4
 8-bit 2-to-1 multiplexer          : 1
 4-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1989 - Unit <dflip>: instances <u1>, <XLXI_6> of unit <dflipflop> are equivalent, second instance is removed

Optimizing unit <alu_4bit> ...

Optimizing unit <fulladdr> ...

Optimizing unit <testcnt> ...
Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block alu_4bit, actual ratio is 4.
WARNING:Xst:1426 - The value init of the FF/Latch tempdis_7 hinder the constant cleaning in the block alu_4bit.
   You should achieve better results by setting this init to 1.
FlipFlop u4_u1_dout has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : alu_4bit.ngr
Top Level Output File Name         : alu_4bit
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 30

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 6
#      1-bit register              : 4
#      5-bit register              : 2
# Multiplexers                     : 4
#      2-to-1 multiplexer          : 4
# Comparators                      : 2
#      5-bit comparator less       : 2
# Xors                             : 9
#      1-bit xor3                  : 9

Cell Usage :
# BELS                             : 70
#      LUT1                        : 4
#      LUT2                        : 25
#      LUT2_D                      : 2
#      LUT3                        : 14
#      LUT3_L                      : 2
#      LUT4                        : 14
#      LUT4_L                      : 6
#      MUXF5                       : 2
#      VCC                         : 1