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Total memory usage is 46328 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.Entity <buff> (Architecture <behavioral>) compiled.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.Architecture behavioral of Entity testcnt is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of I is incompatible with type of temp1.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of O is incompatible with type of ben2.--> Total memory usage is 46328 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.Architecture behavioral of Entity buff is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.Architecture behavioral of Entity testcnt is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of I is incompatible with type of temp.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of O is incompatible with type of ben2.--> Total memory usage is 46328 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.Architecture behavioral of Entity buff is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.Architecture behavioral of Entity testcnt is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of i is incompatible with type of temp1.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of o is incompatible with type of ben2.--> Total memory usage is 46328 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.Architecture behavioral of Entity buff is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.Architecture behavioral of Entity testcnt is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of I is incompatible with type of temp1.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of O is incompatible with type of ben2.--> Total memory usage is 46328 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.Architecture behavioral of Entity buff is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.Architecture behavioral of Entity testcnt is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of I is incompatible with type of temp1.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of O is incompatible with type of ben2.--> Total memory usage is 46328 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.Architecture behavioral of Entity buff is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.Architecture behavioral of Entity testcnt is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 58. Type of i is incompatible with type of temp2.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 58. Type of o is incompatible with type of ben2.--> Total memory usage is 46328 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.Architecture behavioral of Entity buff is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.Architecture behavioral of Entity testcnt is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 58. Type of i is incompatible with type of temp1.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 58. Type of o is incompatible with type of ben2.--> Total memory usage is 46328 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.Architecture behavioral of Entity buff is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.Architecture behavioral of Entity testcnt is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 58. Type of i is incompatible with type of temp1.ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 58. Type of o is incompatible with type of ben2.--> Total memory usage is 46328 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.Architecture behavioral of Entity buff is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.Architecture behavi⌨️ 快捷键说明
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